Charge-scaling multiplier circuit with digital-to-analog converter

Patent metadata

Field	Value
Publication number	US-10658993-B2
Application number	US-201816162435-A
Country	US
Kind code	B2
Filing date	Oct 17, 2018
Priority date	Oct 17, 2018
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a set of scaled capacitors, each capacitor of the set connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to the output of a multiplexor configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.

First claim

What is claimed is:

1. A multiplier circuit fabricated within an integrated circuit (IC), the multiplier circuit configured to draw a product output node to a voltage proportional to a product of two received N-bit binary numbers, the multiplier circuit comprising:
a first set of N inputs configured to receive a first N-bit binary number, each input of the first set of N inputs indexed by an integer bit number “n” corresponding to each input's respective significance, where n is in a range between and including 0 and N−1;
a second set of N inputs configured to receive a second N-bit binary number, each input of the second set of N inputs indexed by the integer bit number “n” corresponding to each input's respective significance;
a local reset device configured to draw, in response to receiving a reset signal, a local product node to ground;
a unity gain amplifier configured to drive a product output node to a voltage equivalent to a voltage on the local product node;
a digital-to-analog converter (DAC) configured to drive, to a DAC output node, an analog voltage that represents a value of the first N-bit binary number, the DAC including:
a voltage divider circuit configured to generate a set of 2 N analog voltages; and
a first analog multiplexer (mux) configured to:
receive, through 2 N analog inputs electrically connected to the voltage divider circuit, the set of 2 N analog voltages;
receive, through a set of N select inputs, the first N-bit binary number; and
drive, to the DAC output node, a DAC output voltage that represents the value of the first N-bit binary number, the DAC output voltage selected, in response to the value of the first N-bit binary number, from the set of 2 N analog voltages; and

a set of N analog muxes, each analog mux of the set of N analog muxes configured to drive, in response to a respective input of the second set of N inputs, to a corresponding analog mux output node, the DAC output voltage;
a set of N scaled capacitors, each capacitor of the set of N scaled capacitors electrically connected to a respective analog mux output node and further electrically connected to the local product node, each capacitor of the set of N scaled capacitors having a capacitance value equal to 2 n * a unit capacitance value (C UNIT ); and
a reference capacitor electrically connected to GND and further electrically connected to the local product node, a value of the reference capacitor equal to C UNIT .

2. The multiplier circuit of claim 1 , wherein the voltage divider circuit includes a set of resistors of equal value configured to provide the set of 2 N analog voltages, wherein the set of 2 N analog voltages are evenly distributed in a range including and between VDD and GND.

3. The multiplier circuit of claim 1 , wherein a voltage of the product output node is in a range between ground (GND) and a supply voltage (Vdd).

4. The multiplier circuit of claim 1 , wherein the local reset device is an N-channel field-effect transistor (NFET).

5. The multiplier circuit of claim 1 , wherein the multiplier circuit receives binary numbers from digital logic circuits within the IC and outputs an analog voltage representing the product of the binary numbers to an analog-to-digital converter (ADC) within the IC.

6. The multiplier circuit of claim 5 , wherein the ADC is selected from the group consisting of: a flash ADC, a resistor ladder ADC, a parallel comparator ADC, a successive-approximation ADC, and a counter type ADC.

7. The multiplier circuit of claim 1 , wherein a supply voltage of the multiplier circuit is in a range between 0.9 V and 1.1 V.

8. The multiplier circuit of claim 1 , wherein the voltage proportional to a product of received N-bit binary numbers is within a voltage range corresponding to +/−1 least significant bit (LSB) of the received N-bit binary numbers.

9. The multiplier circuit of claim 1 , wherein an IC technology is selected from the group consisting of: complementary metal-oxide semiconductor (CMOS) and silicon on insulator (SOI).

10. A multiplier circuit fabricated within an integrated circuit (IC), the multiplier circuit configured to draw a product output node to a voltage proportional to a product of two received N-bit binary numbers, the multiplier circuit comprising:
a first set of N inputs configured to receive a first N-bit binary number, each input of the first set of N inputs indexed by an integer bit number “n” corresponding to each input's respective significance, where n is in a range between and including 0 and N−1;
a second set of N inputs configured to receive a second N-bit binary number, each input of the second set of N inputs indexed by the integer bit number “n” corresponding to each input's respective significance;
a local reset device configured to draw, in response to receiving a reset signal, a local product node to ground;
a digital-to-analog converter (DAC) configured to drive, to a DAC output node, an analog voltage that represents a value of the first N-bit binary number, the DAC including:
a first set of N scaled capacitors, each capacitor of the first set of N scaled capacitors electrically connected to a respective input of the first set of N inputs, and further electrically connected to a scaled node, each capacitor of the first set of N scaled capacitors having a capacitance value equal to 2 n *a unit capacitance value (C UNIT );
a first reference capacitor electrically connected to GND and further electrically connected to the scaled node, a value of the reference capacitor equal to C UNIT *a scaling factor (S); and
a first unity gain amplifier configured to drive the DAC output node to a voltage equivalent to a voltage on the scaled node; and

a set of N analog muxes, each analog mux of the set of N analog muxes configured to drive, in response to a respective input of the second set of N inputs, the DAC output voltage to a corresponding analog mux output node;
a second set of N scaled capacitors, each capacitor of the second set of N scaled capacitors electrically connected to a respective analog mux output node and further electrically connected to the local product node, each capacitor of the second set of N scaled capacitors having a capacitance value equal to 2 n *C UNIT ;
a second reference capacitor electrically connected to GND and further electrically connected to the local product node, a value of the reference capacitor equal to C UNIT ; and
a second unity gain amplifier configured to drive the product output node to a voltage equivalent to a voltage on the local product node.

11. The multiplier circuit of claim 10 , wherein an IC technology is selected from the group consisting of: complementary metal-oxide semiconductor (CMOS) and silicon on insulator (SOI).

12. The multiplier circuit of claim 10 , wherein a value of C UNIT is in a range between 2× and 10× an input capacitance of an analog-to-digital converter (ADC) connected to the product output node.

13. The multiplier circuit of claim 10 , wherein the scaled capacitors and the reference capacitor are selected from the group consisting of: Metal-Insulator-Metal (MIM) capacitors, metal-oxide semiconductor (MOS) capacitors, and trench capacitors.

14. The multiplier circuit of claim 10 , wherein a smallest voltage increment of the voltage, proportional to a product of the received N-bit binary numbers, at the product output node, is greater than an operating voltage of an analog-to-digital converter (ADC) divided by 250.

15. The multiplier circuit of claim 10 , wherein a supply voltage of the multiplier circuit is in a range between 0.9 V and 1.1 V.

Assignees

• IBM

Inventors

• Paulsen David
• Paone Phil
• Paulik George
• Sheets Ii John E
• Erickson Karl

Classifications

• H03K25/02 Primary

  comprising charge storage, e.g. capacitor without polarisation hysteresis · CPC title

• H03M1/206

  using a logic interpolation circuit · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03K19/17724

  Structural details of logic blocks · CPC title

• H03G3/001 Primary

  Digital control of analog signals · CPC title