Superconducting integrated circuit

Patent metadata

Field	Value
Publication number	US-10658424-B2
Application number	US-201615745914-A
Country	US
Kind code	B2
Filing date	Jul 21, 2016
Priority date	Jul 23, 2015
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A superconducting integrated circuit includes at least one superconducting resonator, including a substrate, a conductive layer disposed over a surface of the substrate with the conductive layer including at least one conductive material including a substantially low stress polycrystalline Titanium Nitride (TiN) material having an internal stress less than about two hundred fifty MPa (magnitude) such that the at least one superconducting resonator and/or qubit (hereafter called “device”) is provided as a substantially high quality factor, low loss superconducting device.

First claim

What is claimed is:

1. A superconducting integrated circuit, comprising:
at least a portion of a superconducting resonator and/or qubit, including:
a substrate having first and second opposing surfaces;
a conductive layer having first and second opposing surfaces, wherein the first surface of the conductive layer is disposed over the second surface of the substrate, and the conductive layer includes at least one conductive material, the at least one conductive material including a substantially low stress polycrystalline titanium nitride (TiN) material having an internal stress below about two hundred fifty megapascal (MPa), such that the superconducting resonator and/or qubit is provided as a substantially high quality factor, low loss superconducting resonator and/or qubit;

wherein the conductive layer is provided as a first conductive layer and the superconducting device further includes a second conductive layer having first and second opposing surfaces, wherein the first surface of the second conductive layer is disposed over the second surface of the first conductive layer, and the second conductive layer includes at least one physical superconducting, resistive, and/or tunneling contact extending from the first surface of the second conductive layer to at least a portion of the second surface of the second conductive layer and between the first and second surfaces of the first conductive layer.

2. The integrated circuit of claim 1 further includes a first dielectric layer having first and second opposing surfaces, wherein the first surface of the first dielectric layer is disposed over the second surface of the first conductive layer and the first surface of the second conductive layer is disposed over the second surface of the first dielectric layer, wherein the first conductive layer and the second conductive layer interconnect with at least one superconducting via, said at least one via including at least one substantially low stress; amorphous and/or polycrystalline high quality factor material.

3. The integrated circuit of claim 2 wherein the high quality factor material is a polycrystalline (200)-oriented titanium nitride (TiN) material and/or an amorphous TiN material.

4. The integrated circuit of claim 1 wherein the at least one conductive material additionally or alternatively includes a substantially high stress polycrystalline material having an internal stress between about four hundred megapascal (MPa) and about five gigapascal (GPa), wherein the high stress polycrystalline material is a (200)-oriented titanium nitride (TiN) material.

5. The integrated circuit of claim 1 wherein the conductive layer is annealed at a predetermined rate and temperature during and/or after fabrication of the conductive layer such that the at least one conductive material of the conductive layer changes from a first crystalline orientation and/or crystallinity form of the conductive material to a second, different form of the conductive material to increase the quality factor of the material as determined by at least one superconducting device.

6. The integrated circuit of claim 1 , further comprising at least one of: a Josephson junction, an inductor, a capacitor, and a bias line.

7. The integrated circuit of claim 1 wherein the TiN material is a (200)-oriented polycrystalline.

8. The integrated circuit of claim 1 wherein the TiN material is provided as a (200) oriented single crystal material having a 4-fold symmetry and in-plane rotational alignment.

9. The integrated circuit of claim 1 wherein the substrate is provided from at least one of: silicon; deposited Silicon; silicon having at least one surface with a high resistivity characteristic; oxide coated silicon; oxide etched silicon; oxide etched annealed silicon; glass; aluminum oxide; sapphire; germanium; gallium arsenide; an alloy of silicon and germanium; and indium phosphide.

10. The integrated circuit of claim 1 wherein the second surface of the substrate is a saturated surface and/or an unsaturated surface having at least one of an oxide, hydroxyl, hydride, nitride, fluoride, silicon nitride, hydrogenated nitride, and a hydrogenated fluoride material disposed thereon.

11. The integrated circuit of claim 1 wherein the conductive layer of the superconducting device is electrically and/or mechanically interconnected with a respective conductive layer of a second integrated circuit using a superconducting bump and/or a partially superconducting bump.

12. The integrated circuit of claim 11 wherein the superconducting bump is disposed between a non-superconducting under bump metal (UBM) and a superconducting UBM, between a non-superconducting under bump metal (UBM) and a non-superconducting UBM, or between a superconducting under bump metal (UBM) and a superconducting UBM, said non-superconducting UBM and/or superconducting UBM including at least one conductive material, the at least one conductive material including a polycrystalline titanium nitride (TiN) material or another high quality factor material.

13. The integrated circuit of claim 12 wherein a low stress characteristic of the TiN material and/or the high stress characteristic of the TiN material provides for the superconducting device having an internal quality factor which is greater than about ten to the power of seven at substantially high excitation powers in photon energy regions of about ten to the power of six to about ten to the power of ten, and greater than about ten to the power of six at a substantially low power single photon regime.

14. A superconducting integrated circuit, comprising:
at least a portion of a superconducting resonator and/or qubit, including:
a substrate having first and second opposing surfaces;

a conductive layer having first and second opposing surfaces, wherein the first surface of the conductive layer is disposed over the second surface of the substrate, and the conductive layer includes at least one conductive material, the at least one conductive material including a substantially low stress polycrystalline titanium nitride (TiN) material having an internal stress below about two hundred fifty megapascal (MPa), such that the superconducting resonator and/or qubit is provided as a substantially high quality factor, low loss superconducting resonator and/or qubit; and
at least one qubit and/or superconducting quantum interference device (SQUID) with a portion of the cubit and or SQUID disposed on the second surface of the conductive layer.

Assignees

• Massachusetts Inst Technology

Inventors

• Oliver William D
• Das Rabindra N
• Hover David J
• Rosenberg Danna
• Miloshi Xhovalin
• Bolkhovsky Vladimir
• Yoder Jonilyn L
• Stull Corey W
• Gouker Mark A

Classifications

• H01P7/086 Primary

  Coplanar waveguide resonators (H01P7/088 takes precedence) · CPC title

• H01L39/045

  Electricity · mapped topic

• H01L27/18 Primary

  Electricity · mapped topic

• H01L39/2416

  Electricity · mapped topic

• H01L39/223

  Electricity · mapped topic