Semiconductor devices and semiconductor packages

Patent metadata

Field	Value
Publication number	US-10658319-B2
Application number	US-201916247437-A
Country	US
Kind code	B2
Filing date	Jan 14, 2019
Priority date	Mar 22, 2016
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a semiconductor element;
a substrate; and
a trace disposed adjacent to a surface of the substrate and including a bonding pad, wherein the bonding pad is a contact pad of the trace; and
the bonding pad including:
a first end wall,
a second end wall opposite the first end wall,
a first side wall, and
a second side wall opposite the first side wall,

wherein the first side wall and the second side wall connect the first end wall to the second end wall, and
the first end wall is wider than the second end wall;
wherein the first end wall is closer to the trace than is the second end wall, and the first end wall includes a sloped portion.

2. The semiconductor package of claim 1 , wherein the first end wall is a convex wall comprising a first radius of curvature and the second end wall is a convex wall comprising a second radius of curvature, wherein the first radius of curvature is greater than the second radius of curvature.

3. The semiconductor package of claim 1 , wherein a shape of the first end wall represents an arc of a first circle and a shape of the second end wall represents an arc of a second circle.

4. The semiconductor package of claim 3 , wherein the first circle has a first radius R 1 and the second circle has a second radius R 2 , and wherein a relationship between R 1 and R 2 is specified by the following equation:
θ 1 =sin −1 ((R 1 —R 2 )/D)
wherein the angle θ 1 is from 0° to about 45° and D represents a distance between an origin of the first circle and an origin of the second circle.

5. The semiconductor package of claim 4 , wherein a ratio of R 1 to R 2 is greater than 1:1.

6. The semiconductor package of claim 4 , wherein a ratio of R 1 to R 2 is from about 1.1:1 to about 2.5:1.

7. The semiconductor package of claim 1 , wherein a center line of the bonding pad along a length of the bonding pad forms an angle θ 2 with a center line of the trace.

8. The semiconductor package of claim 7 , wherein the angle θ 2 is from 0° to about 45°.

9. The semiconductor package of claim 1 , wherein one or both of the first side wall and the second side wall are convex.

10. The semiconductor package of claim 1 , wherein one or both of the first side wall and the second side wall incline inwardly, or taper, from the first end wall to the second end wall, such that the first side wall and the second side wall are not parallel.

11. A substrate, comprising:
a trace disposed adjacent to a surface of the substrate and including a bonding pad, wherein the bonding pad is a contact pad of the trace; and
the bonding pad including:
a first end wall,
a second end wall opposite the first end wall,
a first side wall, and
a second side wall opposite the first side wall,

wherein the first side wall and the second side wall connect the first end wall to the second end wall, and
the first end wall is wider than the second end wall;
wherein the first end wall is closer to the trace than is the second end wall, and the first end wall includes a sloped portion.

12. The substrate of claim 11 , wherein the first end wall is a convex wall comprising a first radius of curvature and the second end wall is a convex wall comprising a second radius of curvature, wherein the first radius of curvature is greater than the second radius of curvature.

13. The substrate of claim 11 , wherein a shape of the first end wall represents an arc of a first circle and a shape of the second end wall represents an arc of a second circle.

14. The substrate of claim 13 , wherein the first circle has a first radius R 1 and the second circle has a second radius R 2 , and wherein a relationship between R 1 and R 2 is specified by the following equation:
θ 1 =sin −1 ((R 1 —R 2 )/D)
wherein the angle θ 1 is from 0° to about 45° and D represents a distance between an origin of the first circle and an origin of the second circle.

15. The substrate of claim 14 , wherein a ratio of R 1 to R 2 is greater than 1:1.

16. The substrate of claim 14 , wherein a ratio of R 1 to R 2 is from about 1.1:1 to about 2.5:1.

17. The substrate of claim 11 , wherein a center line of the bonding pad along a length of the bonding pad forms an angle θ 2 with a center line of the trace.

18. The substrate of claim 17 , wherein the angle θ 2 is from 0° to about 45°.

19. The substrate of claim 18 wherein one or both of the first side wall and the second side wall incline inwardly, or taper, from the first end wall to the second end wall, such that the first side wall and the second side wall are not parallel.

20. The substrate of claim 11 , wherein one or both of the first side wall and the second side wall incline inwardly, or taper, from the first end wall to the second end wall, such that the first side wall and the second side wall are not parallel.

Assignees

• Advanced Semiconductor Eng

Inventors

• Hung Chih-Pin
• Chen Dao-Long
• Chiu Ying-Ta
• Yang Ping-Feng

Classifications

• H01L24/13 Primary

  Electricity · mapped topic

• H01L2224/16145

  Electricity · mapped topic

• H01L2224/13083

  Electricity · mapped topic

• H01L2224/13017

  Electricity · mapped topic

• H01L2224/81815

  Electricity · mapped topic