Atomic layer deposition and etch for reducing roughness

Patent metadata

Field	Value
Publication number	US-10658174-B2
Application number	US-201715820110-A
Country	US
Kind code	B2
Filing date	Nov 21, 2017
Priority date	Nov 21, 2017
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.

First claim

What is claimed is:

1. A method comprising:
etching, in a plasma chamber, to a first depth of a substrate to form a plurality of features at the first depth;
depositing, in the plasma chamber, a first passivation layer on sidewalls of the plurality of features by atomic layer deposition (ALD), wherein a step coverage of the first passivation layer in the plurality of features is greater than about 95%; and
etching, in the plasma chamber, the plurality of features to a second depth greater than the first depth, wherein the first passivation layer is configured to substantially prevent lateral etching of the sidewalls and substantially limit sidewall roughness after etching to the second depth.

2. The method of claim 1 , wherein one or both of an LWR and LER value of the sidewalk is equal to or less than about 1.5 nm after etching the plurality of features to the second depth.

3. The method of claim 1 , wherein the plurality of features include shallow trench isolation (STI) features.

4. The method of claim 1 , wherein a depth-to-width aspect ratio of each of the plurality of features is equal to or greater than 10:1.

5. The method of claim 1 , wherein a critical dimension of the plurality of features is equal to or less than about 20 nm.

6. The method of claim 1 , wherein each of the first depth and the second depth is equal to or greater than about 100 nm.

7. The method of claim 1 , wherein the plurality of features include one or more isolated features in an isolated feature region and one or more dense features in a dense feature region having a greater feature density than the isolated feature region, wherein a thickness of the first passivation layer along the sidewalls of the plurality of features is substantially similar in the isolated feature region and the dense feature region.

8. The method of claim 1 , wherein the plurality of features are defined by a plurality of structures, wherein one or more first structures includes a first material and one or more second structures includes a second material different than the first material, wherein a thickness of the first passivation layer along the sidewalk of the plurality of features is substantially similar for the one or more first structures and the one or more second structures.

9. The method of claim 1 , wherein the plurality of features are defined by a plurality of structures, each of the structures including silicon, germanium, or combinations thereof.

10. The method of claim 1 , further comprising:
depositing, in the plasma chamber, a second passivation layer on the sidewalls of the plurality of features by ALD; and
etching, in the plasma chamber, the plurality of features to a third depth greater than the second depth in the substrate, wherein the second passivation layer is configured to substantially prevents lateral etching of the sidewalk and substantially limit sidewall roughness after etching the plurality of features to the third depth.

11. The method of claim 1 , wherein the operations of depositing by ALD and etching the plurality of features in the plasma chamber are performed without introducing a vacuum break in between operations.

12. The method of claim 1 , wherein the first passivation layer includes silicon oxide (SiO x ).

Assignees

• Lam Res Corp

Inventors

• Zhou Xiang
• Ansari Naveed
• Kimura Yoshie
• Li Si-Yi Yi
• Sultana Kazi
• Mani Radhika
• Zhang Duming
• Kazi Haseeb
• Xu Chen
• Brooks Mitchell
• Upadhyaya Ganesh

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H01L21/473

  Electricity · mapped topic

• H01L21/0337

  Electricity · mapped topic

• H01L21/0217

  Electricity · mapped topic

• H01L21/0228 Primary

  Electricity · mapped topic