Semiconductor memory device and method of erasing data of partial page and overwriting partial page with predetermined data

Patent metadata

Field	Value
Publication number	US-10658042-B2
Application number	US-201615758021-A
Country	US
Kind code	B2
Filing date	Aug 4, 2016
Priority date	Sep 15, 2015
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A semiconductor memory device and method of erasing data are disclosed. In one example, a semiconductor memory device includes a block including a plurality of pages and a controller that controls writing, erasing, and reading of data. Each of the pages includes a plurality of memory cells each being changeable to a number of states. In a case of erasing only a partial page of the plurality of pages, the controller overwrites the partial page with predetermined data that causes state change only by one stage.

First claim

The invention claimed is:

1. A semiconductor memory device, comprising:
a block including a plurality of pages;
a controller configured to control writing, erasing, and reading of data, wherein
each of the pages includes a plurality of memory cells each being changeable to one of four or eight states, and
in a case of erasing only a partial page of the plurality of pages, the controller overwrites the partial page with predetermined data that causes state change only by one stage; and
a plurality of word lines and a plurality of bit lines, wherein
the memory cells are disposed at respective intersections of the plurality of word lines and the plurality of bit lines, and
data of a plurality of pages is stored on each one of the plurality of word lines,
wherein
the plurality of pages on each one of the word lines include first to third pages, and
the controller is configured to
overwrite all of the memory cells in the first page or all of the memory cells in the second page with data of “1” as the predetermined data in a case where the first page or the second page as the partial page is erased, and
overwrite all of the memory cells in the third page with data of “0” as the predetermined data in a case where the third page as the partial page is erased.

2. The semiconductor memory device according to claim 1 , wherein the controller reads out written data in the plurality of pages including the partial page, and generates the predetermined data on the basis of the readout data.

3. A semiconductor memory device comprising:
a block including a plurality of pages;
a controller configured to control writing, erasing, and reading of data, wherein
each of the pages includes a plurality of memory cells each being changeable to one of four or eight states, and
in a case of erasing only a partial page of the plurality of pages, the controller overwrites the partial page with predetermined data that causes state change only by one stage; and
a plurality of word lines and a plurality of bit lines, wherein
the memory cells are disposed at respective intersections of the plurality of word lines and the plurality of bit lines, and
data of a plurality of pages is stored on each one of the plurality of word lines, wherein
the plurality of pages on each of the word lines include a first page and a second page, and
in a case where the first page as the partial page is erased, the controller overwrites all of the memory cells in the first page with, as the predetermined data, data of a logical product of the first page and the second page.

4. A semiconductor memory device comprising:
a block including a plurality of pages;
a controller configured to control writing, erasing, and reading of data, wherein
each of the pages includes a plurality of memory cells each being changeable to one of four or eight states, and
in a case of erasing only a partial page of the plurality of pages, the controller overwrites the partial page with predetermined data that causes state change only by one stage; and
a plurality of word lines and a plurality of bit lines, wherein
the memory cells are disposed at respective intersections of the plurality of word lines and the plurality of bit lines, and
data of a plurality of pages is stored on each one of the plurality of word lines, wherein
the plurality of pages include a first page and a second page, and
the controller is configured to
overwrite all of the memory cells in the second page with data of “1” as the predetermined data in a case where the second page as the partial page is erased before the first page is erased, and
overwrite all of the memory cells in the first page with, as the predetermined data, data of a logical product of the first page and the second page in a case where the first page as the partial page is further erased after the second page is erased.

5. A semiconductor memory device comprising:
a block including a plurality of pages;
a controller configured to control writing, erasing, and reading of data, wherein
each of the pages includes a plurality of memory cells each being changeable to one of four or eight states, and
in a case of erasing only a partial page of the plurality of pages, the controller overwrites the partial page with predetermined data that causes state change only by one stage; and
a plurality of word lines and a plurality of bit lines, wherein
the memory cells are disposed at respective intersections of the plurality of word lines and the plurality of bit lines, and
data of a plurality of pages is stored on each one of the plurality of word lines, wherein
the plurality of pages include a first page and a second page, and
the controller is configured to
overwrite all of the memory cells in the first page with, as the predetermined data, data of a logical product of the first page and the second page in a case where the first page is erased as the partial page, and
overwrite all of the memory cells in the second page with data of “0” as the predetermined data in a case where the second page as the partial page is further erased thereafter.

6. The semiconductor memory device according to claim 1 , wherein the state of the memory cell is changeable among four states.

7. The semiconductor memory device according to claim 1 , wherein the state of the memory cell is changeable among eight states.

8. A method of erasing data in a semiconductor memory device, the semiconductor memory device including a block that includes a plurality of pages, and each of the pages including a plurality of memory cells each being changeable to one of four or eight states, the method comprising:
in a case of erasing a partial page of the plurality of pages, overwriting the partial page with predetermined data that causes state change only by one stage, wherein the plurality of pages include first to third pages, and wherein
overwriting the partial page comprises
overwriting all of the memory cells in the first page or all of the memory cells in the second page with data of a first value as the predetermined data in a case where the first page or the second page as the partial page is erased, and
overwriting all of the memory cells in the third page with data of a second value as the predetermined data in a case where the third page as the partial page is erased,
wherein the first value is one and the second value is zero.

9. A semiconductor memory device comprising:
a block including a plurality of pages;
a controller configured to control writing, erasing, and reading of data, wherein
each of the pages includes a plurality of memory cells each being changeable to one of four or eight states, and
in a case of erasing only a partial page of the plurality of pages, the controller overwrites the partial page with predetermined data that causes state change only by one stage, wherein
the plurality of pages include first to third pages, and
the controller is configured to
overwrite all of the memory cells in the first page or all of the memory cells in the second page with data of a first value as the predetermined data in a case where the first page or the second page as the partial page is erased, and
overwrite all of the memory cells in the third page with data of a second value as the predetermined data in a case where the third page as the partial page is erased, and
wherein the first value is one and the second value is zero.

Assignees

• Sony Corp

Inventors

• Date Kazuyuki

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G06F2212/7205

  Cleaning, compaction, garbage collection, erase control · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title