Display device, gate drive circuit, shift register and control method for the same

Patent metadata

Field	Value
Publication number	US-10657866-B2
Application number	US-201916252992-A
Country	US
Kind code	B2
Filing date	Jan 21, 2019
Priority date	Apr 10, 2018
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A display device, a gate drive circuit, a shift register and its control method are described. The shift register includes: an input circuit, a first output circuit, a second output circuit, a control circuit and an output drive circuit, wherein the output drive circuit is connected to a second signal input terminal, a pull-up node, a control terminal of the second output circuit and a low voltage signal terminal, and is configured to write a voltage of the second signal input terminal into the control terminal of the second output circuit and superimpose a voltage of the pull-up node onto the control terminal of the second output circuit under the control of a second input signal provided at the second signal input terminal, such that the second output circuit is fully turned on to ensure that it has good output capability when working at a low temperature.

First claim

What is claimed is:

1. A shift register, comprising:
an input circuit connected to a first signal input terminal and a pull-up node, and configured to write a voltage of the first signal input terminal to the pull-up node responsive to a first input signal provided at the first signal input terminal;
a first output circuit connected to the pull-up node, a first clock signal terminal and a first signal output terminal, and configured to write a voltage of the first clock signal terminal to the first signal output terminal responsive to a voltage of the pull-up node;
a second output circuit connected to the first clock signal terminal and a second signal output terminal, and configured to write the voltage of the first clock signal terminal to the second signal output terminal responsive to a voltage of a control terminal of the second output circuit;
a control circuit connected to a second clock signal terminal, the pull-up node, a reset signal terminal, a low voltage signal terminal and the first signal output terminal, and configured to control voltages of the first signal output terminal and the pull-up node responsive to a second clock signal provided at the second clock signal terminal and a voltage of the reset signal terminal;
an output drive circuit connected to a second signal input terminal, the pull-up node, a control terminal of the second output circuit and the low voltage signal terminal, and configured to write a voltage of the second signal input terminal to the control terminal of the second output circuit and provide the voltage of the pull-up node to the control terminal of the second output circuit responsive to a second input signal provided at the second signal input terminal.

2. The shift register according to claim 1 , wherein the control circuit comprises:
a pull-down circuit which is connected to the reset signal terminal, the low voltage signal terminal, the pull-up node and the first signal output terminal, and is configured to write a voltage of the low voltage signal terminal to the first signal output terminal and the pull-up node responsive to a voltage of the reset signal terminal;
a pull-down control circuit which is connected to the second clock signal terminal, the pull-up node, a pull-down node and the low voltage signal terminal, and is configured to write a voltage of the second clock signal terminal to the pull-down node responsive to the second clock signal provided at the second clock signal terminal and to write the voltage of the low voltage signal terminal to the pull-down node responsive to the voltage of the pull-up node;
a first denoising circuit which is connected to the pull-down node, the pull-up node, the low voltage signal terminal and the first signal output terminal, and is configured to denoise the pull-up node and the first signal output terminal responsive to a voltage of the pull-down node.

3. The shift register according to claim 2 , wherein the control circuit further comprises:
a second denoising circuit which is connected to the pull-up node, the first signal input terminal, the low voltage signal terminal, the first signal output terminal and the second clock signal terminal, and is configured to denoise the first signal output terminal based on the second clock signal provided at the second clock signal terminal.

4. The shift register according to claim 3 , wherein the second denoising circuit comprises:
a twelfth transistor comprising a first terminal of the twelfth transistor connected to the first signal output terminal, a second terminal of the twelfth transistor connected to the low voltage signal terminal, and a control terminal of the twelfth transistor connected to the second clock signal terminal; and
a thirteenth transistor comprising a first terminal of the thirteenth transistor connected to the first signal input terminal, a second terminal of the thirteenth transistor connected to the pull-up node, and a control terminal of the thirteenth transistor connected to the second clock signal terminal.

5. The shift register according to claim 2 ,
wherein the pull-down control circuit comprises a first pull-down control sub-circuit and a second pull-down control sub-circuit,
wherein the second pull-down control sub-circuit is connected to the second clock signal terminal, a pull-down control node and the pull-down node, and is configured to change a voltage of the pull-down control node responsive to the second clock signal provided at the second clock signal terminal,
wherein the first pull-down control sub-circuit is connected to the pull-down control node, the pull-up node, the pull-down node and the low voltage signal terminal, and is configured to change the voltage of the pull-down node responsive to the pull-up node and the pull-down control node,
wherein the second pull-down control sub-circuit comprises a sixth transistor and a seventh transistor,
wherein a control terminal of the sixth transistor and a first terminal of the sixth transistor are connected to the second clock signal terminal,
wherein a second terminal of the sixth transistor is connected to the pull-down control node,
wherein a first terminal of the seventh transistor is connected to the pull-down node,
wherein a second terminal of the seventh transistor is connected to the second clock signal terminal,
wherein a control terminal of the seventh transistor is connected to the pull-down control node,
wherein the first pull-down control sub-circuit comprises an eighth transistor and a ninth transistor,
wherein a first terminal of the eighth transistor is connected to the low voltage signal terminal,
wherein a second terminal of the eighth transistor is connected to the pull-down node,
wherein a control terminal of the eighth transistor is connected to the pull-up node,
wherein a first terminal of the ninth transistor is connected to the pull-down control node,
wherein a second terminal of the ninth transistor is connected to the low voltage signal terminal, and
wherein a control terminal of the ninth transistor is connected to the pull-up node.

6. The shift register according to claim 2 , wherein the first denoising circuit comprises:
a tenth transistor comprising a first terminal of the tenth transistor connected to the low voltage signal terminal, a second terminal of the tenth transistor connected to the first signal output terminal, and a control terminal of the tenth transistor connected to the pull-down node; and
an eleventh transistor comprising a first terminal of the eleventh transistor connected to the low voltage signal terminal, a second terminal of the eleventh transistor connected to the pull-up node, and a control terminal of the eleventh transistor connected to the pull-down node.

7. The shift register according to claim 2 , wherein the pull-down circuit comprises:
a fourteenth transistor comprising a first terminal of the fourteenth transistor connected to the first signal output terminal, a second terminal of the fourteenth transistor connected to the low voltage signal terminal, and a control terminal of the fourteenth transistor connected to the reset signal terminal;
a fifteenth transistor comprising a first terminal of the fifteenth transistor connected to the pull-up node, a second terminal of the fifteenth transistor connected to the low voltage signal terminal and a control terminal of the fifteenth transistor connected to the reset signal terminal.

8. The shift register according to claim 1 , wherein the output drive circuit comprises:
a first transistor comprising a first terminal of the first transistor and a control terminal of the first transistor connected to the second signal input terminal and a second terminal of the first transistor connected to a

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Qian Xianrui
• Chen Yuting
• Wang Zixuan
• Li Bo
• Li Fei

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title