Performing texturing operations for sets of plural execution threads in graphics processing systems

US10657699B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-10657699-B1
Application numberUS-201816214060-A
CountryUS
Kind codeB1
Filing dateDec 8, 2018
Priority dateDec 8, 2018
Publication dateMay 19, 2020
Grant dateMay 19, 2020

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Abstract

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When a texture mapper in a graphics processor is to perform a texturing operation for a set of plural execution threads together, the texture mapper determines whether the texturing operation for the set of plural threads can be performed together with the texturing operation for another set of plural execution threads for which a texturing operation is required. When the texture mapper determines that the texturing operations for the sets of plural execution threads can be performed together, it performs the texturing operations for the sets of plural threads together, but when it determines that the texturing operation for the set of plural threads cannot be performed together with the texturing operation for another set of plural execution threads, it performs the texturing operation for the set of plural execution threads alone.

First claim

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The invention claimed is: 1. A method of operating a graphics processor, the graphics processor comprising: a programmable fragment shader operable to execute graphics fragment shading programs to perform fragment shading operations; and a texture mapper operable to perform graphics texturing operations in response to requests for graphics texturing operations from the fragment shader; wherein: the fragment shader processes graphics fragments by executing fragment shader programs using respective execution threads for sampling positions of a render output being generated by the graphics processor; and the fragment shader is operable to, when it encounters a graphics texturing instruction in a fragment shader program that it is executing for a thread: request the texture mapper to perform a graphics texturing operation for a set of plural threads that are executing the graphics texturing instruction in the fragment shader program; and the texture mapper is operable to, in response to a request from the fragment shader to perform a texturing operation for a set of plural execution threads that are executing a graphics texturing instruction in a shader program: perform the texturing operation for the set of plural execution threads together; the method comprising: when the texture mapper is to perform a texturing operation for a set of plural execution threads together, the texture mapper: determining whether the texturing operation for the set of plural threads can be performed together with the texturing operation for another set of plural execution threads for which a texturing operation is required; and when it is determined that the texturing operations for the sets of plural execution threads can be performed together, performing the texturing operations for the sets of plural threads together; and when it is determined that the texturing operation for the set of plural threads cannot be performed together with the texturing operation for another set of plural execution threads for which a texturing operation is required, performing the texturing operation for the set of plural execution threads alone. 2. The method of claim 1 , wherein each set of plural threads comprises four threads. 3. The method of claim 1 , comprising performing the texturing operation for two sets of plural execution threads together. 4. The method of claim 1 , wherein: the texture mapper determines whether the texturing operation for a set of plural threads can be performed together with the texturing operation for another set of plural threads based on the types of texturing operation that the two sets of plural threads are performing. 5. The method of claim 1 , wherein: the texture mapper determines that the texturing operation for a set of plural threads can be performed together with the texturing operation for another set of plural threads when the two sets of plural threads are performing the same texturing operation, reading the same texture(s), and using the same control parameters for their texturing operations. 6. The method of claim 1 , wherein: the fragment shader processes execution threads as respective thread groups; and the texture mapper determines that the texturing operation for a set of plural threads can be performed together with the texturing operation for another set of plural threads when the two sets of plural threads belong to the same thread group. 7. The method of claim 1 , wherein the texturing requests sent to the texture mapper indicate for the set of plural execution threads for which the texturing request is sent, whether the set of plural execution threads can be combined with another set of plural execution threads when performing the texturing operation. 8. The method of claim 1 , wherein the texture mapper is operable to: take as an input plural sets of plural execution threads in the same cycle; and determine whether the texturing operations of the input sets of plural execution threads can be performed together; and the method comprises: when the texture mapper determines that the texturing operations of the input sets of plural execution threads can be performed together, the texture mapper performing the texturing operations for the input sets of plural execution threads together starting in the next processing cycle; and when the texture mapper determines that the texturing operations for the input sets of plural execution threads should not be performed together, the texture mapper performing the texturing operation for one of the sets of plural execution threads starting in the next processing cycle, whilst stalling the other set or sets of plural execution threads for that cycle, and then performing the texturing operation for another of the sets of plural execution threads starting in the next processing cycle. 9. The method of claim 1 , wherein: the texture mapper is operable to take as an input one set of plural execution threads in the same cycle; and the method comprises the texture mapper when it receives an input set of plural execution threads for a texturing operation: stalling that set of plural execution threads for one cycle to see whether its texturing operation can be combined with the texturing operation for the next input set of plural execution threads; and when the texture mapper determines that the texturing operations of the input plural sets of plural execution threads can be performed together, performing the texturing operations for both input sets of plural execution threads together starting in the next processing cycle; and when the texture mapper determines that the texturing operations for the sets of plural execution threads should not be performed together, performing the texturing operation for one of the input sets of plural execution threads starting in the next cycle on its own. 10. The method of claim 1 , wherein the texture mapper maintains a record of pending texture mapping operations to be performed and the record of pending texture mapping operations is configured such that an entry in the record can store all the record data required for performing a texture mapping operation for plural sets of plural threads for which a texture mapping operation is to be performed together. 11. The method of claim 1 , wherein the texture mapper comprises a coordinate computation circuit that is operable to determine the texel positions in a texture to be fetched for a texturing operation from sampling position coordinates for which the texture mapping operation is to be performed; and the coordinate computation circuit is in the form of four coordinate computation pipelines, that are each operable to process one sampling position coordinate when determining the texels to be fetched for a texturing operation for a sampling position. 12. A graphics processor comprising: a programmable fragment shader circuit operable to execute graphics fragment shading programs to perform fragment shading operations; and a texture mapper circuit operable to perform graphics texturing operations in response to requests for graphics texturing operations from the fragment shader circuit; wherein: the fragment shader circuit processes graphics fragments by executing fragment shader programs using respective execution threads for sampling positions of a render output being generated by the graphics processor; and the fragment shader circuit is operable to, when it encounters a graphics texturing instruction in a fragment shader program that it is executing for a thread: request the texture mapper circuit to perform a graphics texturing operation for a set of plural threads that are executing the graphics textu

Assignees

Inventors

Classifications

  • G06T15/04Primary

    Texture mapping · CPC title

  • General purpose rendering architectures · CPC title

  • Program initiating; Program switching, e.g. by interrupt · CPC title

  • Processor architectures; Processor configuration, e.g. pipelining · CPC title

  • using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

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What does patent US10657699B1 cover?
When a texture mapper in a graphics processor is to perform a texturing operation for a set of plural execution threads together, the texture mapper determines whether the texturing operation for the set of plural threads can be performed together with the texturing operation for another set of plural execution threads for which a texturing operation is required. When the texture mapper determi…
Who is the assignee on this patent?
Advanced Risc Mach Ltd
What technology area does this patent fall under?
Primary CPC classification G06T15/04. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 19 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).