Predictive spatial digital design of experiment for advanced semiconductor process optimization and control

Patent metadata

Field	Value
Publication number	US-10657214-B2
Application number	US-201816155773-A
Country	US
Kind code	B2
Filing date	Oct 9, 2018
Priority date	Oct 9, 2018
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

This disclosure describes methods and systems for building a spatial model to predict performance of processing chamber, and using the spatial model to converge faster to a desired process during the process development phase. Specifically, the method obtains virtual metrology (VM) data from sensors of the chamber and on-board metrology (OBM) data from devices on the wafers; obtains in-line metrology data from precision scanning electron microscope (SEM); and also obtains an empirical process model for a given process. The empirical process model is calibrated by using the in-line metrology data as reference. A predictive model is built by refining the empirical process model by a machine-learning engine that receives customized metrology data and outputs one or more spatial maps of the wafer for one or more dimensions of interest across the wafer without physically processing any further wafers, i.e. by performing spatial digital design of experiment (Spatial DoE).

First claim

What is claimed is:

1. A computer-implemented method, comprising:
performing a physical design of experiment (DoE) based on a known initial recipe by processing a finite number of wafers to generate virtual metrology (VM) data and on-board metrology (OBM) data related to one or more dimensions of interest associated with features of devices fabricated on the finite number of wafers, wherein the VM data includes time traces of one or more process variables collected from sensors of a processing equipment;
obtaining in-line metrology data from a scanning electron microscope (SEM);
obtaining an empirical process model for a process and the processing equipment;
calibrating the empirical process model by using the in-line metrology data as reference;
combining the VM, OBM and in-line metrology data to generate customized metrology data; and
building a predictive model by refining the empirical process model by a machine-learning engine that receives the customized metrology data and outputs one or more spatial maps of a wafer for one or more dimensions of interest across the wafer, wherein the predictive model is to perform spatial digital DoE without physically processing any further wafers, and wherein the spatial digital DoE comprises a multi-constraint optimization of the process for the processing equipment and for the one or more dimensions of interest across the wafer.

2. The method of claim 1 , wherein the customized metrology data additionally includes transmission electron microscope (TEM) data.

3. The method of claim 1 , wherein the predictive model, in an inverse mode, is to recommend virtual recipes for processing the wafer.

4. The method of claim 1 , wherein the predictive model is to identify a process window within a process space for which process-induced variation of the one or more dimensions of interest is within an acceptable limit.

5. The method of claim 1 , wherein the machine-learning engine is further to receive information about a specific process and one or more specific equipment where the process is to be performed.

6. The method of claim 1 , further comprising:
validating the predictive model using further metrology data obtained from processing another set of physical wafers.

7. The method of claim 1 , wherein the predictive model is to correlate the customized metrology data with one or more critical knob settings within a process space.

8. The method of claim 7 , wherein machine-learning techniques are used to identify combined effect of the one or more critical knobs on the one or more dimensions of interest.

9. The method of claim 1 , wherein each wafer comprises a full wafer or a portion thereof.

10. A non-transistory computer readable medium comprising instructions, which, when executed by a processor, cause the processor to perform operations for building a machine-learning based predictive model for spatial digital design of experiment (DoE), the operations comprising:
obtaining an initial recipe based on knowledge of a semiconductor process;
processing a first set of wafers by changing a plurality of variables of the semiconductor process around the initial recipe to identify critical knobs of a processing equipment that influence one or more dimensions of interest of a device fabricated on the first set of wafers;
screening results from the processing of the first set of wafers to determine an optimum number of wafers needed to cover interaction of the identified critical knobs within a process space;
processing a second set of wafers by varying the identified critical knobs within the process space, wherein the second set comprises the optimum number of wafers;
collecting virtual metrology (VM) data related to the one or more dimensions of interest from sensors of the processing equipment during the processing of the second set of wafers, wherein the VM data includes time traces of one or more process variables;
collecting on-board metrology (OBM) data related to the one or more dimensions of interest from the second set of wafers;
collecting in-line metrology data related to the one or more dimensions of interest by performing e-beam inspection and metrology on at least some of the wafers from the second set of wafers;
combining the VM, OBM and in-line metrology data to generate customized metrology data related to the one or more dimensions of interest;
determining correlation of the customized metrology data with the identified critical knob settings within the process space; and
building, by a machine-learning engine, predictive model using the determined correlation to predict a spatial distribution of the one or more dimensions of interest when various knobs associated with the semiconductor process are virtually varied within the process space, wherein the predicted spatial distribution of the one or more dimensions of interest provides for performing spatial digital DoE without having to physically process any further wafers to optimize the semiconductor process for the given processing equipment.

11. The non-transitory computer readable medium of claim 10 , wherein the customized metrology data additionally includes transmission electron microscope (TEM) data.

12. The non-transitory computer readable medium of claim 10 , wherein the predictive model, in an inverse mode, is to recommend virtual recipes for processing the wafer.

13. The non-transitory computer readable medium of claim 10 , wherein the predictive model is to identify a process window within the process space for which process-induced variation of the one or more dimensions of interest is within an acceptable limit.

14. The non-transitory computer readable medium of claim 10 , wherein the machine-learning engine is further to receive information about a specific process and one or more specific processing equipment where the process is to be performed.

15. The non-transitory computer readable medium of claim 10 , the operations further comprising:
validating the predictive model using further metrology data obtained from processing another set of physical wafers.

16. The non-transitory computer readable medium of claim 10 , wherein machine-learning techniques are used to identify combined effect of the one or more critical knobs on the one or more dimensions of interest.

17. The non-transitory computer readable medium of claim 10 , wherein each wafer comprises a full wafer or a portion thereof.

18. A system, comprising:
a memory; and
a processor, operatively coupled with the memory, to:
obtain virtual metrology (VM) data and on-board metrology (OBM) data related to one or more dimensions of interest associated with features of devices fabricated on a finite number of wafers, wherein the VM data and the OBM data are generated by performing a physical design of experiment (DoE) based on a known initial recipe used to process the finite number of wafers, wherein the VM data includes time traces of one or more process variables collected from sensors of a processing equipment;
obtain in-line metrology data from a scanning electron microscope (SEM);
obtain an empirical process model for a process and the processing equipment;
calibrate the empirical process model by using the in-line metrology data as reference;
combine the VM, OBM and in-line metrology data to generate customized metrology data; and
build a predictive model by refining the empirical process model by a machine-learning engine that receives the customized metrology data and outputs one or more spatial maps of the wafer for the one or more dimensions of interest a

Assignees

• Applied Materials Inc

Inventors

• Banna Samer
• Cantwell Dermot
• Bishara Waheb

Classifications

• G06N20/00 Primary

  Machine learning · CPC title

• G06F30/333

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title

• G06N5/04

  Inference or reasoning models · CPC title

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F17/5068 Primary

  Physics · mapped topic