Semiconductor device

Patent metadata

Field	Value
Publication number	US-10656201-B2
Application number	US-201815970057-A
Country	US
Kind code	B2
Filing date	May 3, 2018
Priority date	Jun 29, 2017
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

According to one embodiment, a semiconductor device performs processing based on a user program by using a user program, which is used in a normal mode, as an analysis program and making a plurality of peripheral circuits having the same function operate in lock-step where the plurality of peripheral circuits operate in the identical manner, and makes failure diagnosis of the peripheral circuits by determining match or mismatch of a plurality of analysis information respectively obtained from the plurality of peripheral circuits operating in lock-step.

First claim

What is claimed is:

1. A semiconductor device comprising:
a program execution unit configured to execute a user program;
a peripheral circuit group configured to include a plurality of peripheral circuits having the same circuit configuration and controlled by the program execution unit; and
an analysis subsystem configured to perform defect analysis of the peripheral circuit group based on the user program in accordance with an operation instruction from the program execution unit,
wherein the analysis subsystem includes
an analysis setting register configured to store analysis execution set values at least including an analysis target peripheral circuit set value specifying an analysis target peripheral circuit group including a plurality of analysis target peripheral circuits to be used for the defect analysis among the peripheral circuits included in the peripheral circuit group and a comparison target peripheral circuit set value specifying a comparison target peripheral circuit to be compared among the peripheral circuits included in the analysis target peripheral circuit group,
a module selector configured to control an operating state of the peripheral circuit group so that all of the analysis target peripheral circuits included in the analysis target peripheral circuit group operate based on the analysis target peripheral circuit set value,
an arbiter configured to distribute, to the plurality of peripheral circuits included in the analysis target peripheral circuit group, the operation instruction output from the program execution unit to the comparison target peripheral circuit based on the comparison target peripheral circuit set value and the analysis target peripheral circuit set value and then extracts, as analysis information, data output from the plurality of peripheral circuits included in the analysis target peripheral circuit group in response to the given operation instruction, and transmits the data output from the comparison target peripheral circuit to the program execution unit, and
a comparison unit configured to compare information obtained from each of the plurality of peripheral circuits included in the analysis target peripheral circuit group based on the analysis information, and output error information identifying a location of a bit indicating a different value.

2. The semiconductor device according to claim 1 , wherein the comparison unit compares an address signal indicating a destination of the operation instruction output from the program execution unit, the address signal being applied to each of the plurality of peripheral circuits included in the analysis target peripheral circuit group, and outputs, as the error information, address error information identifying a location of a bit value indicating a different address value.

3. The semiconductor device according to claim 1 , wherein the comparison unit operates based on an operating clock applied to the analysis target peripheral circuit group among operating clocks applied to the peripheral circuit group.

4. The semiconductor device according to claim 1 , wherein the program execution unit includes
a CPU core configured to output, to the analysis setting register, the analysis execution set values at least including the analysis target peripheral circuit set value, the comparison target peripheral circuit set value, and a fetch address identifying a location of an instruction to be executed among instructions in the user program, and
an analysis core configured to execute the user program based on the fetch address included in the analysis execution set values stored by the CPU core into the analysis setting register.

5. The semiconductor device according to claim 4 , wherein, during an analysis mode where the analysis core executes the user program based on the analysis execution set values, the CPU core stops execution of the user program until execution of the user program by the analysis core stops, or executes the user program and makes peripheral circuits not included in the analysis target peripheral circuit group operate.

6. The semiconductor device according to claim 1 , wherein
in a normal operation mode where the analysis execution set values are not stored in the analysis setting register, the module selector outputs an individual module address signal that puts each of the plurality of peripheral circuits into an operating state individually based on a module address signal supplied from the program execution unit, and
in an analysis mode where the analysis execution set values are stored in the analysis setting register, the module selector outputs an analysis target selection signal that puts all of the analysis target peripheral circuits included in the analysis target peripheral circuit group into an operating state, regardless of the module address signal.

7. The semiconductor device according to claim 1 , wherein
in a normal operation mode where the analysis execution set values are not stored in the analysis setting register, the module selector shifts a module address signal supplied from the program execution unit by a shift amount determined for each peripheral circuit to be accessed, and generates a peripheral address signal specifying the peripheral circuit individually, and
in an analysis mode where the analysis execution set values are stored in the analysis setting register, the module selector outputs a plurality of module address signals corresponding to all of the peripheral circuits included in the analysis target peripheral circuit group from the module address signal.

8. The semiconductor device according to claim 1 , comprising:
an interrupt arbiter configured to arbitrate a plurality of interrupt requests respectively issued from the plurality of peripheral circuits when an abnormality occurs in the peripheral circuit, and notifies the program execution unit of any one of the plurality of interrupt requests.

9. A semiconductor device comprising:
a first CPU core configured to execute a user program;
a peripheral circuit group configured to include a plurality of peripheral circuits having the same circuit configuration and controlled by the first CPU core; and
an analysis subsystem configured to perform defect analysis of the peripheral circuit group based on the user program in accordance with an instruction from the first CPU core,
wherein the analysis subsystem includes
an analysis setting register configured to store analysis execution set values at least including an analysis target peripheral circuit set value specifying an analysis target peripheral circuit group including a plurality of analysis target peripheral circuits to be used for the defect analysis among the peripheral circuits included in the peripheral circuit group and a comparison target peripheral circuit set value specifying a comparison target peripheral circuit to be compared among the peripheral circuits included in the analysis target peripheral circuit group,
a module selector configured to control an operating state of the peripheral circuit group so that all of the analysis target peripheral circuits included in the analysis target peripheral circuit group operate based on the analysis target peripheral circuit set value,
an arbiter configured to extract analysis information containing at least one of an address and data input to and output from the plurality of peripheral circuits included in the analysis target peripheral circuit group based on the analysis target peripheral circuit set value, and transmit the data output from the comparison target peripheral circuit to a circuit located upstream based on the comparison target peripheral circuit set value, and
a comparison unit configured to compare information ob

Assignees

• Renesas Electronics Corp

Inventors

• Lee Takuya
• Kokubun Tetsuya
• Nakadai Yutaka
• Shiozawa Kenji
• Nakamura Yoshihide

Classifications

• G06F15/78

  comprising a single central processing unit · CPC title

• G06F11/202

  where processing functionality is redundant (redundant communication control functionality G06F11/2005, redundant storage control functionality G06F11/2089) · CPC title

• G01R31/3167 Primary

  Testing of combined analog and digital circuits {(testing ADC's H03M1/1071)} · CPC title

• G06F11/27 Primary

  Built-in tests · CPC title

• G06F11/18 Primary

  using passive fault-masking of the redundant circuits {(error detection by comparing the output of redundant processing systems with continued operation after detection of the error G06F11/165)} · CPC title