Memory device and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-10651373-B2
Application number	US-201816194124-A
Country	US
Kind code	B2
Filing date	Nov 16, 2018
Priority date	Sep 28, 2018
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

A method for forming an integrated circuit is provided. The method includes forming a dielectric layer over a cell region and a logic region of a substrate; forming a resistance switching layer over the dielectric layer; performing at least one etch process to pattern the resistance switching layer into a plurality of resistance switching elements in the cell region, in which a first portion of the dielectric layer in the logic region is less etched by the etch process than a second portion of the dielectric layer in the cell region.

First claim

What is claimed is:

1. A method for forming an integrated circuit, comprising:
forming a dielectric layer over a cell region and a logic region of a substrate;
forming a resistance switching layer over the dielectric layer; and
performing at least one etch process to pattern the resistance switching layer into at least one resistance switching element in the cell region, wherein a first portion of the dielectric layer in the logic region is less etched by the etch process than a second portion of the dielectric layer in the cell region.

2. The method of claim 1 , wherein the first portion of the dielectric layer is etched by the etch process later than the second portion of the dielectric layer.

3. The method of claim 1 , wherein the etch process is performed such that the first portion of the dielectric layer has a thickness greater than that of a thinnest part of the second portion of the dielectric layer.

4. The method of claim 1 , further comprising:
forming a mask layer over the resistance switching layer before performing the etching process, wherein the mask layer has a first portion in the logic region and a second portion in the cell region, and the first portion of the mask layer is thicker than the second portion of the mask layer; and
patterning the mask layer before performing the etching process.

5. The method of claim 4 , wherein forming the mask layer comprises:
depositing an oxide mask material over the resistance switching layer; and
thinning a portion of the oxide mask material in the cell region.

6. The method of claim 1 , further comprising:
removing the first portion of the dielectric layer while remaining the second portion of the dielectric layer after the etch process.

7. The method of claim 6 , further comprising:
forming an interlayer dielectric layer over the logic region after removing the first portion of the dielectric layer; and
forming a metallization pattern in the interlayer dielectric layer over the logic region.

8. The method of claim 1 , further comprising:
forming a bottom via in the dielectric layer in the cell region before forming the resistance switching layer.

9. A method for forming an integrated circuit, comprising:
forming a resistance switching layer over a cell region and a logic region of a substrate;
forming a mask layer over the resistance switching layer;
thinning a portion of the mask layer over the cell region of the substrate;
patterning the mask layer; and
patterning the resistance switching layer to form a plurality of resistance switching elements in the cell region of the substrate.

10. The method of claim 9 , wherein patterning the mask layer is performed to form a plurality of masks over the cell region and an extending mask portion over the logic region of the substrate, wherein a thickness of the masks is greater than a thickness of the extending mask portion.

11. The method of claim 9 , further comprising:
forming a top electrode layer over the resistance switching layer before forming the mask layer; and
etching the top electrode layer through the patterned mask layer to form a plurality of top electrodes in the cell region of the substrate and an extending portion in the logic region of the substrate.

12. The method of claim 11 , wherein the patterned mask layer has a higher etch resistance to etching the top electrode layer than that of the top electrode layer.

13. The method of claim 11 , wherein etching the top electrode layer removes a portion of the patterned mask layer in the logic region of the substrate.

14. The method of claim 11 , wherein patterning the resistance switching layer comprises:
etching the resistance switching layer to remove the extending portion of the top electrode layer.

15. The method of claim 14 , wherein the top electrode layer has a higher etch resistance to etching the resistance switching layer than that of the resistance switching layer.

16. A method for forming an integrated circuit, comprising:
depositing a resistance switching layer over a substrate;
depositing a top electrode layer over the resistance switching layer;
patterning the top electrode layer into a plurality of top electrodes and an extending portion; and
patterning the resistance switching layer to into a plurality of resistance switching elements respectively below the top electrodes through an etching process, wherein the etching process is performed to remove the extending portion.

17. The method of claim 16 , wherein the etching process is performed such that the top electrodes remain over the resistance switching elements, respectively.

18. The method of claim 16 , wherein patterning the top electrode layer is performed such that the extending portion is thinner than the top electrodes.

19. The method of claim 16 , wherein patterning the top electrode layer is performed such that the extending portion is spaced apart from the top electrodes.

20. The method of claim 16 , wherein patterning the resistance switching layer is performed such that a resistor element spaced apart from the resistance switching elements is formed, wherein the resistor element is thinner than the resistance switching elements.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Tai-Yen
• Huang Chien-Chung
• Chen Yu-Shu
• Yang Sin-Yi
• Wang Chen-Jung
• Lin Han-Ting
• Ting Chih-Yuan
• Shieh Jyu-Horng
• Wei Hui-Hsien

Classifications

• H01L27/228

  Electricity · mapped topic

• H01L27/224

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic

• H01L43/12 Primary

  Electricity · mapped topic