Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10651301-B2
Application number	US-201815980635-A
Country	US
Kind code	B2
Filing date	May 15, 2018
Priority date	Jun 30, 2017
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

In one embodiment, a semiconductor device includes a semiconductor substrate having an upper surface, a trench electrode placed inside a trench formed on the upper surface, and a trench insulating film placed between the trench electrode and the semiconductor substrate, and the semiconductor substrate includes a drift layer, a floating layer for electric field reduction, a hole barrier layer, a body layer and an emitter layer, and the emitter layer, the body layer and the hole barrier layer are separated from the drift layer by the floating layer for electric field reduction, and a path of a carrier passing through an inverted layer formed in the body layer includes the body layer, the hole barrier layer, a non-inverted region of the floating layer for electric field reduction, and the drift layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having an upper surface;
a first trench electrode placed inside a first trench formed on the upper surface;
a second trench electrode placed inside a second trench formed on the upper surface;
a third trench electrode placed inside a third trench formed on the upper surface;
a first trench insulating film placed between the first trench electrode and the semiconductor substrate;
a second trench insulating film placed between the second trench electrode and the semiconductor substrate; and
a third trench insulating film placed between the third trench electrode and the semiconductor substrate,
wherein the semiconductor substrate includes:
a first semiconductor layer of a first conductivity type,
a floating layer of a second conductivity type placed on the first semiconductor layer, a lower end of each of the first, second and third trench electrodes reaching the floating layer,
a barrier layer of the first conductivity type placed on the floating layer and being in contact with the first, second and third trench insulating films,
a second semiconductor layer of the second conductivity type placed on the barrier layer and being in contact with the first, second and third trench insulating films, and
a third semiconductor layer of the first conductivity type placed on the second semiconductor layer,

wherein the third semiconductor layer, the second semiconductor layer and the barrier layer are separated from the first semiconductor layer by the floating layer,
wherein a path of a carrier passing through an inverted layer formed in the second semiconductor layer includes the second semiconductor layer, the barrier layer, a non-inverted region of the floating layer, and the first semiconductor layer,
wherein a gate voltage is applied to the first trench electrode for forming an inverted region in a part of the second semiconductor layer in contact with the trench insulating film,
wherein an emitter voltage is applied to the second and third trench electrodes for establishing continuity between the first semiconductor layer and the third semiconductor layer, and
wherein the lower end of each of the first, second and third trench electrodes is covered with the floating layer via each of the first, second and third trench insulating films such that the first, second and third trench insulating films are directly in contact with the floating layer.

2. The semiconductor device according to claim 1 ,
wherein the first trench electrode is arranged between the second trench electrode and the third trench electrode, and
wherein the third semiconductor layer, the second semiconductor layer and the barrier layer are arranged between the first trench electrode and the second trench electrode, and between the first trench electrode and the third trench electrode.

3. The semiconductor device according to claim 2 , further comprising:
a fourth trench electrode placed inside a fourth trench formed on the upper surface;
a fifth trench electrode placed inside a fifth trench formed on the upper surface;
a fourth trench insulating film placed between the fourth trench electrode and the semiconductor substrate; and
a fifth trench insulating film placed between the fifth trench electrode and the semiconductor substrate,
wherein the second trench electrode is arranged between the fourth trench electrode and the first trench electrode,
wherein the third trench electrode is arranged between the fifth trench electrode and the first trench electrode, and
wherein the fourth and fifth trench electrodes are not covered with the floating layer.

4. The semiconductor device according to claim 2 ,
wherein side surface of the second trench electrode, positioned opposite to the first trench electrode, is covered with the floating layer via the second trench insulating film, and
wherein side surface of the third trench electrode, positioned opposite to the first trench electrode, is covered with the floating layer via the third trench insulating film.

5. The semiconductor device according to claim 1 , wherein impurity concentration of the barrier layer is higher than impurity concentration of the first semiconductor layer.

6. The semiconductor device according to claim 1 , wherein impurity concentration of the floating layer is lower than impurity concentration of the second semiconductor layer.

Assignees

• Renesas Electronics Corp

Inventors

• Kanda Ryo
• Matsuura Hitoshi

Classifications

• H01L29/7397 Primary

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic

• H01L29/407

  Electricity · mapped topic

• H01L29/0804

  Electricity · mapped topic

• H01L29/66348

  Electricity · mapped topic