Semiconductor device and a method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10651289-B2
Application number	US-201816195102-A
Country	US
Kind code	B2
Filing date	Nov 19, 2018
Priority date	Dec 28, 2015
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode, wherein:
the first gate electrode includes a first lower metal layer and a first upper metal layer,
the first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer fully filling a space formed by the first underlying metal layer,
the first underlying metal layer consists of Ti,
the first bulk metal layer consists of TiN, and
a bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.

2. The semiconductor device of claim 1 , wherein the first upper metal layer includes at least one of Co, W, Ti, Al, and Cu.

3. The semiconductor device of claim 1 , wherein the first upper metal layer is made of Co.

4. The semiconductor device of claim 1 , further comprising a cap insulating layer disposed on the first gate electrode.

5. The semiconductor device of claim 4 , further comprising sidewall spacers disposed on opposing side faces of the first gate electrode and the cap insulating layer.

6. The semiconductor device of claim 5 , further comprising:
an interlayer dielectric (ILD) layer and an etching stop layer disposed between the interlayer dielectric layer and one of the sidewall spacers.

7. The semiconductor device of claim 6 , the etching stop layer is one of SiN, SiCN and SiOCN.

8. The semiconductor device of claim 6 , further comprising a source/drain epitaxial layer in contact with one of the sidewall spacers,
wherein the etching stop layer is in contact with an upper surface of the source/drain epitaxial layer.

9. The semiconductor device of claim 8 , further comprising a source/drain contact passing through the ILD layer and the etching stop layer and in contact with the source/drain epitaxial layer.

10. The semiconductor device of claim 8 , further comprising a gate contact passing through the cap insulating layer and in contact with the first upper metal layer.

11. The semiconductor device of claim 1 , further comprising:
a second FET including a second gate dielectric layer and a second gate electrode, wherein:
the second gate electrode includes a second lower metal layer and a second upper metal layer,
the second lower metal layers includes a second underlying metal layer in contact with the second gate dielectric layer, a third underlying metal layer and a second bulk metal layer fully filing a space formed by the third underlying metal layer,
the second underlying metal layer consists of TiN,
the third underlying metal layer consists of Ti,
the second bulk metal layer consists of TiN, and
a bottom of the second upper metal layer is in contact with an upper surface of the second underlying metal layer, an upper surface of the third underlying metal layer and an upper surface of the second bulk metal layer.

12. The semiconductor device of claim 1 , further comprising:
a second field effect transistor (FET) including a second gate dielectric layer and a second gate electrode, wherein:
the second gate electrode includes a second lower metal layer and a second upper metal layer,
the second lower metal layer includes a second underlying metal layer in contact with the second gate dielectric layer and a second bulk metal layer fully filling a space formed by the second underlying metal layer,
the second underlying metal layer consists of Ti,
the second bulk metal layer consists of TiN,
a bottom of the second upper metal layer is in contact with an upper surface of the second underlying metal layer and an upper surface of the second bulk metal layer, and
a width of the second gate electrode is greater than a width of the first gate electrode, along a lateral direction perpendicular to a lateral direction in which the first and second gate electrodes extend.

13. A semiconductor device, comprising:
an FET including a gate dielectric layer and a gate electrode, wherein:
the gate electrode includes a lower metal layer and a upper metal layer,
the lower metal layers includes a first underlying metal layer in contact with the gate dielectric layer, a second underlying metal layer and a bulk metal layer fully filing a space formed by the second underlying metal layer,
the first underlying metal layer consists of TiN,
the second underlying metal layer consists of Ti,
the bulk metal layer consists of TiN, and
a bottom of the upper metal layer is in contact with an upper surface of the first underlying metal layer, an upper surface of the second underlying metal layer and an upper surface of the bulk metal layer.

14. The semiconductor device of claim 13 , wherein the upper metal layer includes at least one of Co, W, Ti, Al, and Cu.

15. The semiconductor device of claim 13 , further comprising:
a cap insulating layer disposed on the gate electrode; and
sidewall spacers disposed on opposing side faces of the gate electrode and the cap insulating layer.

16. The semiconductor device of claim 15 , further comprising:
an interlayer dielectric (ILD) layer and an etching stop layer disposed between the interlayer dielectric layer and one of the sidewall spacers.

17. The semiconductor device of claim 16 , the etching stop layer is one of SiCN and SiOCN.

18. The semiconductor device of claim 16 , further comprising a source/drain epitaxial layer in contact with one of the sidewall spacers,
wherein the etching stop layer is in contact with an upper surface of the source/drain epitaxial layer.

19. A semiconductor device, comprising:
a first FET including a first gate dielectric layer and a first gate electrode; and
a second FET including a second gate dielectric layer and a second gate electrode, wherein:
a gate length of the first FET is smaller than a gate length of the second FET,
the first gate electrode includes a first lower metal layer and a first upper metal layer,
the first lower metal layers includes a first underlying metal layer in contact with the first gate dielectric layer, a second underlying metal layer disposed on the first underlying metal layer and a first bulk metal layer fully filing a space formed by the second underlying metal layer,
the second gate electrode includes a second lower metal layer and a second upper metal layer,
the second lower metal layer includes a third underlying metal layer in contact with the second gate dielectric layer and a second bulk metal layer fully filling a space formed by the third underlying metal layer,
the first underlying metal layer consists of TiN,
the second underlying metal layer consists of Ti,
the first bulk metal layer consists of TiN,
the third underlying metal layer consists of Ti, and
the second bulk metal layer consists of TiN.

20. The semiconductor device of claim 19 , wherein:
the first gate electrode consists of the first underlying metal layer, the second underlying metal layer, the first bulk metal layer and the first upper metal layer, and
the second gate electrode consist of the third underlying metal layer, the second bulk metal layer and the second upper metal layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiou Yao-De
• Chen Janet
• Yeh Jeng-Ya

Classifications

• H01L29/66545 Primary

  Electricity · mapped topic

• H01L21/823842

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic

• H01L29/4958

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic