Semiconductor device and a method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10134872-B2
Application number	US-201615063346-A
Country	US
Kind code	B2
Filing date	Mar 7, 2016
Priority date	Dec 28, 2015
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A source/drain region is formed. A first insulating layer is formed over the dummy gate structure and the source/drain region. A gate space is formed by removing the dummy gate structure. The gate space is filled with a first metal layer. A gate recess is formed by removing an upper portion of the filled first metal layer. A second metal layer is formed over the first metal layer in the gate recess. A second insulating layer is formed over the second metal layer in the gate recess.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a dummy gate structure over a substrate, the dummy gate structure including a dummy gate dielectric layer, a dummy gate electrode layer and sidewall spacers;
forming a source/drain region including an epitaxial layer;
forming an etching stop layer over the dummy gate structure and the source/drain region;
forming a first insulating layer over the etching stop layer;
forming a gate space by removing the dummy gate electrode layer and the dummy gate dielectric layer so as to form a gate space;
filling the gate space with a first metal layer;
forming a gate recess by removing an upper portion of the filled first metal layer;
forming a second metal layer on a top of the first metal layer, from which the upper portion has been removed, in the gate recess; and
forming a second insulating layer over the second metal layer in the gate recess,
wherein the etching stop layer and one of the sidewall spacers are disposed between the first insulating layer and the first and second metal layers.

2. The method of claim 1 , wherein a material of the first metal layer is different from a material of the second metal layer.

3. The method of claim 1 , wherein the material of the first metal layer is TiN.

4. The method of claim 1 , wherein the material of the second metal layer includes at least one of Co, W, Ti, Al, and Cu.

5. The method of claim 1 , further comprising:
forming a gate dielectric layer in the gate space; and
forming a third metal layer on the gate dielectric layer in the gate space before forming the first metal layer,
wherein a bottom of the second metal layer is in contact with an upper surface of the first metal layer and an upper surface of the third metal layer.

6. The method of claim 5 , wherein a material of the third metal layer is Ti.

7. The method of claim 1 , wherein the forming the second metal layer over the first metal layer includes:
forming a blanket layer of a metal material for the second metal layer in the gate recess and over the first insulating layer; and
removing upper portions of the metal material so that an upper surface of the second metal layer is located below an upper surface of the first insulating layer.

8. The method of claim 1 , wherein the forming the second metal layer over the first metal layer includes:
forming a metal material for the second metal layer in the gate recess so that the metal material partially fills the gate recess and an upper surface of the second metal layer is located below an upper surface of the first insulating layer.

9. The method of claim 1 , wherein the etching stop layer is one of SiN, SiCN and SiOCN and is in contact with the source/drain region.

10. The method of claim 1 , wherein the material of the second metal layer is Co.

11. The method of claim 1 , wherein the second metal layer is selectively formed on the top of the first metal layer only in the gate space.

12. A method of manufacturing a semiconductor device, the method comprising:
forming a first dummy gate structure and a second dummy gate structure over a substrate, each of the first dummy gate structure and the second dummy gate structure including a dummy gate dielectric layer, a dummy gate electrode layer and sidewall spacers;
forming source/drain regions including an epitaxial layer;
forming an etching stop layer over the first and second dummy gate structures and the source/drain region;
forming a first insulating layer over the etching stop layer;
forming a first gate space and a second gate space by removing the dummy gate electrode layer and the dummy gate dielectric layer from the first and second dummy gate structures;
forming a first metal layer in the first gate space;
forming a second metal layer in the first and second gate spaces;
after forming the first and second metal layers, filling the first and second gate spaces with a third metal layer;
forming a first gate recess by removing upper portions of the first, second and third metal layers formed in the first gate space, and forming a second gate recess by removing upper portions of the first and third metal layers formed in the second gate space;
forming a first gate electrode and a second gate electrode by forming fourth metal layers on tops of the first, second and third metal layers, from which the upper portions have been removed, in the first gate recess and on tops of the first and third metal layers, from which the upper portions have been removed, in the second gate recess; and
forming second insulating layers over the fourth metal layers in the first and second gate recess,
wherein the etching stop layer and one of the sidewall spacers are disposed between the first insulating layer and the first gate electrode.

13. The method of claim 12 , wherein:
the first metal layer is TiN,
the second metal layer is Ti,
the third metal layer is TiN, and
the fourth metal layer includes at least one of Co, W, Ti, Al, and Cu.

14. The method of claim 13 , wherein:
in the first gate electrode, a bottom of the fourth metal layer is in contact with upper surfaces of the first, second and third metal layers, and
in the second gate electrode, a bottom of the fourth metal layers is in contact with upper surfaces of the first and third metal layers.

15. The method of claim 12 , wherein the forming fourth metal layers includes:
forming a blanket layer of a metal material for the fourth metal layers in the first and second gate recesses and over the first insulating layer; and
removing upper portions of the metal material so that upper surfaces of the fourth metal layers are located below an upper surface of the first insulating layer.

16. The method of claim 12 , wherein the forming the fourth metal layers includes
forming a metal material for the fourth metal layers in the first and second gate recesses so that the metal material partially fills the first and second gate recesses.

17. A method of manufacturing a semiconductor device, the method comprising:
forming a first dummy gate structure, a second dummy gate structure and a third dummy gate structure over a substrate, the first, second and third dummy gate structures extending in a first lateral direction, each of the first, second and third dummy gate structures including a dummy gate dielectric layer, a dummy gate electrode layer and sidewall spacers;
forming source/drain regions including an epitaxial layer;
forming an etching stop layer over the first, second and third dummy gate structures and the source/drain region;
forming a first insulating layer over the etching stop layer;
forming a first gate space, a second gate space and a third gate space by removing the dummy gate electrode layer and the dummy gate dielectric layer from the first, second and third dummy gate structures, respectively;
forming a first metal layer in the first gate space;
forming a second metal layer in the first, second and third gate spaces;
after forming the first and second metal layers, filling the first, second and third gate spaces with a third metal layer;
forming a first gate recess by removing upper portions of the first, second and third metal layers formed in the first gate space, forming a second gate recess by removing upper portions of the first and third metal layers formed in the second gate space, and forming a third gate recess by removing upper portions of the first and third metal layers formed in the third gate space;
forming a first gate electrode, a second gate electrod

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiou Yao-De
• Chen Janet
• Yeh Jeng-Ya David

Classifications

• H01L21/823842

  Electricity · mapped topic

• H01L29/4958

  Electricity · mapped topic

• H01L21/823437

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic