Method for avoiding IL regrown in a HKMG process

Patent metadata

Field	Value
Publication number	US-10651285-B2
Application number	US-201715429192-A
Country	US
Kind code	B2
Filing date	Feb 10, 2017
Priority date	Dec 16, 2016
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

The present disclosure addresses and solves the current problem of oxygen accumulation in IL after an HKMG stack is formed. A fabrication method is provided for fabricating high-k/metal gate semiconductor device by forming at least one Titanium (Ti) layer between multiple HK layers. A high-k/metal gate semiconductor device including at least one TiO2 layer between multiple HK layers is also provided.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate comprising silicon material; and
a gate electrode stack formed on the substrate, wherein the gate electrode stack comprising:
an interfacial layer formed on an upper surface of the substrate;
a first high-k dielectric layer formed on the interfacial layer;
a first titanium (Ti) only layer formed on the first high-k dielectric layer;
a second high-k dielectric layer formed on the first titanium only layer such that the first titanium only layer is not oxidized by a deposition process before the second high-k dielectric layer is formed on the first titanium only layer; and wherein the first titanium only layer is oxidized by oxygen from or through the first and the second high-k dielectric layer;
a third high-k dielectric layer formed on the second high-k dielectric layer;
a second titanium (Ti) only layer formed on the third high-k dielectric layer; and
a fourth high-k dielectric layer formed on the second titanium only layer such that the second titanium only layer is not oxidized by a deposition process before the fourth high-k dielectric layer is formed on the second titanium only layer; and wherein the second titanium only layer is oxidized by oxygen from or through the third and the fourth high-k dielectric layers.

2. The semiconductor device of claim 1 , wherein the gate electrode stack is formed using a high-k metal-gate gate-first process.

3. The semiconductor device of claim 1 , wherein the gate electrode stack is formed using a high-k metal-gate gate-last process.

4. The semiconductor device of claim 1 , wherein the first high-k dielectric layer is characterized by a thickness less than 1 nm.

5. The semiconductor device of claim 1 , wherein the second high-k dielectric layer is characterized by a thickness less than 1 nm.

6. The semiconductor device of claim 1 , wherein the second high-k dielectric layer is characterized by a thickness less than a thickness of the first high-k dielectric layer.

7. The semiconductor device of claim 1 , wherein the first and second high-k dielectric layers are characterized by a combined thickness less than 2 nm.

8. The semiconductor device of claim 1 , wherein the gate electrode stack further comprising at least one more composite structure, wherein the composite structure is formed by below method:
forming a new first high-k dielectric layer on previous high-k dielectric layer;
forming a new titanium (Ti) only layer on the new first high-k dielectric layer; and
forming a new second high-k dielectric layer on the new titanium only layer such that the new titanium only layer is not oxidized by a deposition process before the new second high-k dielectric layer is formed on the new titanium only layer; and wherein the new titanium only layer is oxidized by oxygen from or through the new first and the new second high-k dielectric layers.

9. The semiconductor device of claim 8 , wherein total thickness of all high-k dielectric layers is less than 2 nm.

10. The semiconductor device of claim 8 , wherein total thickness of all oxidized titanium only layers is less than 0.5 nm.

11. A method for fabricating a high-k metal-gate, the method comprising:
forming a substrate comprising silicon material; and
forming a gate electrode stack on the substrate, wherein forming the gate electrode stack comprising:
forming an interfacial layer on an upper surface of the substrate;
forming a first high-k dielectric layer on the interfacial layer;
forming a first titanium only layer on the first high-k dielectric layer without oxidizing the first titanium only layer;
forming a second high dielectric layer on the first titanium only layer such that the first titanium only layer is not oxidized by a deposition process before the second high-k dielectric layer is formed on the first titanium only layer; and wherein the first titanium only layer is oxidized by oxygen from or through the first and the second high-k dielectric layers;
forming a third high-k dielectric layer on the second high-k dielectric layer;
forming a second titanium (Ti) only layer on the third high-k dielectric layer; and
forming a fourth high-k dielectric layer on the second titanium only layer such that the second titanium only layer is not oxidized by a deposition process before the fourth high-k dielectric layer is formed on the second titanium only layer; and wherein the second titanium only layer is oxidized by oxygen from or through the third and the fourth high-k dielectric layers.

12. The method of claim 11 , wherein the gate electrode stack is formed using a high-k metal-gate gate-first process.

13. The method of claim 11 , wherein the gate electrode stack is formed using a high-k metal-gate gate-last process.

14. The method of claim 11 , wherein the first high-k dielectric layer is characterized by a thickness less than 1 nm.

15. The method of claim 11 wherein the second high-k dielectric layer is characterized by a thickness less than 1 nm.

16. The method of claim 11 , wherein the second high-k dielectric layer is characterized by a thickness less than a thickness of the first high-k dielectric layer.

17. The method of claim 11 , wherein the first and second high-k dielectric layers are characterized by a combined thickness less than 2 nm.

18. The method of claim 11 , wherein forming the gate electrode stack further comprising forming at least one more composite structure, wherein the composite structure is formed by below method:
forming a new first high-k dielectric layer on previous high-k dielectric layer;
forming a new titanium (Ti) only layer on the new first high-k dielectric layer; and
forming a new second high-k dielectric layer on the new titanium only layer such that the new titanium only layer is not oxidized by a deposition process before the new second high-k dielectric layer is formed on the new titanium only layer; and wherein the new titanium only layer is oxidized by oxygen from or through the new first and the new second high-k dielectric layers.

19. The method of claim 18 , wherein total thickness of all high-k dielectric layers is less than 2 nm.

20. The method of claim 18 , wherein total thickness of all oxidized titanium only layers is less than 0.5 nm.

Assignees

• Shanghai Huali Microelect Corp

Inventors

• Liu Yingming
• Bao Yu
• Zhou Haifeng
• Fang Jingxun

Classifications

• H10D64/0135

  by deposition of a layer, e.g. metal, metal compound or polysilicon, followed by transformation thereof into the insulator · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H01L29/66545

  Electricity · mapped topic

• H01L29/517 Primary

  Electricity · mapped topic

• H01L29/49

  Electricity · mapped topic