Manufacturing method of display substrate, display substrate and display device
US-12062711-B2 · Aug 13, 2024 · US
US10651212B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10651212-B2 |
| Application number | US-201916388349-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 18, 2019 |
| Priority date | Nov 13, 2014 |
| Publication date | May 12, 2020 |
| Grant date | May 12, 2020 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A thin film transistor array substrate, a method for manufacturing the same and a display device are provided. The TFT array substrate includes: a substrate, and a gate electrode, a common electrode, a gate insulation layer, an active layer, a source electrode and a drain electrode arranged on the substrate. The TFT array substrate further includes: a pixel electrode, arranged on the gate insulation layer, overlapped with and jointed to the drain electrode; a passivation layer, arranged on the gate insulation layer and a channel between the source and drain electrodes; and a common electrode line, arranged on a plane identical to the pixel electrode.
Opening claim text (preview).
What is claimed is: 1. A thin film transistor (TFT) array substrate, comprising: a substrate, and a gate electrode, a common electrode, a gate insulation layer, an active layer, a source electrode and a drain electrode arranged on the substrate, wherein the TFT array substrate further comprises: a pixel electrode, arranged on the gate insulation layer, overlapped with and jointed to the drain electrode; a passivation layer, arranged on the gate insulation layer and a channel between the source and drain electrodes; and a common electrode line, arranged in a layer different from the common electrode and arranged on a plane identical to the pixel electrode. 2. The TFT array substrate according to claim 1 , wherein the common electrode line is made of a same material as the pixel electrode. 3. The TFT array substrate according to claim 2 , further comprising: a transparent conductive thin film protective portion, arranged between the gate electrode and the substrate, wherein the transparent conductive thin film protective portion is arranged at a same layer and made of a same material as the common electrode; a common electrode line connection portion, arranged on the common electrode and comprising a first transparent conductive layer and a gate metal layer, wherein the common electrode is connected to the common electrode line via the common electrode line connection portion. 4. The TFT array substrate according to claim 3 , further comprising: a gate electrode protective layer, arranged between the gate electrode and the gate insulation layer; wherein the common electrode line connection portion further comprises a second transparent conductive layer arranged at a same layer and made of a same material as the gate electrode protective layer. 5. The TFT array substrate according to claim 2 , further comprising: a source electrode protective portion covering the source electrode and arranged at a same layer and made of a same material as the pixel electrodes. 6. A display device, comprising: a thin film transistor (TFT) array substrate; wherein the thin film transistor array substrate comprises: a substrate, and a gate electrode, a common electrode, a gate insulation layer, an active layer, a source electrode and a drain electrode arranged on the substrate, wherein the TFT array substrate further comprises: a pixel electrode, arranged on the gate insulation layer, overlapped with and jointed to the drain electrode; a passivation layer, arranged on the gate insulation layer and a channel between the source and drain electrodes; and a common electrode line, arranged in a layer different from the common electrode and arranged on a plane identical to the pixel electrode. 7. The display device according to claim 6 , wherein the common electrode line is made of a same material as the pixel electrode. 8. The display device according to claim 7 , wherein the TFT array substrate further comprises: a transparent conductive thin film protective portion, arranged between the gate electrode and the substrate, wherein the transparent conductive thin film protective portion is arranged at a same layer and made of a same material as the common electrode; a common electrode line connection portion, arranged on the common electrode and comprising a first transparent conductive layer and a gate metal layer, wherein the common electrode is connected to the common electrode line via the common electrode line connection portion. 9. The display device according to claim 8 , wherein the TFT array substrate further comprises: a gate electrode protective layer, arranged between the gate electrode and the gate insulation layer; wherein the common electrode line connection portion further comprises a second transparent conductive layer arranged at a same layer and made of a same material as the gate electrode protective layer. 10. The display device according to claim 7 , wherein the TFT array substrate further comprises: a source electrode protective portion covering the source electrode and arranged at a same layer and made of a same material as the pixel electrodes.
Photolithographic processes · CPC title
by chemical means · CPC title
using masks for conductive or resistive materials · CPC title
Electricity · mapped topic
Electricity · mapped topic
Related publications grouped by family.
Answers are generated from the same data shown on this page.