Array substrate, display panel and display device

Patent metadata

Field	Value
Publication number	US-10651205-B2
Application number	US-201815951466-A
Country	US
Kind code	B2
Filing date	Apr 12, 2018
Priority date	Feb 8, 2017
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

An array substrate and a display device are provided. The array substrate includes a base substrate; a first active layer, located on the base substrate; a first insulating layer, located on the first active layer and the base substrate; a gate electrode, located at a side of the first insulating layer away from the first active layer; a second insulating layer, located on the gate electrode and the first insulating layer; a second active layer, located on the second insulating layer away from the gate electrode; a first drain electrode and a first source electrode, being in partial contact with the first active layer, respectively; a second drain electrode and a second source electrode, being in partial contact with the second active layer, respectively; and a pixel electrode, the first drain electrode and the second drain electrode are electrically connected, the first source electrode and the second source electrode are electrically connected, and the pixel electrode is electrically connected with at least one of the first drain electrode and the second drain electrode. The array substrate can improve the responding speed and charging efficiency, and avoid increasing the aperture opening ratio at the same time.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate;
a first active layer, located on the base substrate;
a first insulating layer, located on the first active layer and the base substrate;
a gate electrode, located at a side of the first insulating layer away from the first active layer;
a second insulating layer, located on the gate electrode and the first insulating layer;
a second active layer, located at a side of the second insulating layer away from the gate electrode;
a first drain electrode and a first source electrode, each being in partial contact with the first active layer;
a second drain electrode and a second source electrode, each being in partial contact with the second active layer; and
a pixel electrode,
wherein the first drain electrode and the second drain electrode are electrically connected, the first source electrode and the second source electrode are electrically connected, and the pixel electrode is electrically connected with at least one of the first drain electrode and the second drain electrode,
the array substrate further comprises:
a passivation layer, located at a side of the second drain electrode and the second source electrode away from the second active layer;
a third via hole, located in the first insulating layer, the second insulating layer, the second drain electrode, and the passivation layer and partially exposing the first drain electrode;
a first conductive structure, located in the third via hole to electrically connect the first drain electrode and the second drain electrode;
a fourth via hole, located in the first insulating layer, the second insulating layer, the second source electrode, and the passivation layer and partially exposing the first source electrode; and
a second conductive structure, located in the fourth via hole to electrically connect the first source electrode and the second source electrode.

2. The array substrate according to claim 1 , wherein an orthographic projection of the gate electrode on the base substrate falls into an orthographic projection of the first active layer and the second active layer on the base substrate.

3. The array substrate according to claim 1 , further comprising:
a first via hole, located in the first insulating layer and the second insulating layer and partially exposing the first drain electrode, wherein a part of the second drain electrode penetrates through the first via hole to reach the first drain electrode so that the second drain electrode and the first drain electrode are electrically connected with each other.

4. The array substrate according to claim 3 , further comprising:
a second via hole, located in the first insulating layer and the second insulating layer and partially exposing the first source electrode, wherein a part of the second source electrode penetrates through the second via hole to reach the first source electrode so that the second source electrode and the first source electrode are electrically connected with each other.

5. The array substrate according to claim 4 ,
wherein the pixel electrode is located between the second drain electrode and the passivation layer and is in partial contact with the second drain electrode.

6. The array substrate according to claim 5 , further comprising:
a common electrode at a side of the passivation layer away from the base substrate; and
a common electrode line in a same layer as the gate electrode,
wherein a part of the common electrode penetrates a via hole in the passivation layer and the second insulating layer to reach the common electrode line so that the common electrode and the common electrode line are electrically connected with each other, and the common electrode and the pixel electrode are at least partially overlapped with each other in a direction perpendicular to the base substrate.

7. The array substrate according to claim 5 , further comprising:
a fifth via hole, located in the passivation layer and partially exposing a portion of the pixel electrode that is in contact with the second drain electrode, wherein the first conductive structure is further located in the fifth via hole.

8. The array substrate according to claim 1 , wherein the pixel electrode comprises the first conductive structure.

9. The array substrate according to claim 2 , further comprising:
a first via hole, located in the first insulating layer and the second insulating layer and partially exposing the first drain electrode, wherein a part of the second drain electrode penetrates through the first via hole to reach the first drain electrode so that the second drain electrode and the first drain electrode are electrically connected with each other.

10. The array substrate according to claim 9 , further comprising:
a second via hole, located in the first insulating layer and the second insulating layer and partially exposing the first source electrode, wherein a part of the second source electrode penetrates through the second via hole to reach the first source electrode so that the second source electrode and the first source electrode are electrically connected with each other.

11. The array substrate according to claim 7 , further comprising:
a sixth via hole, located in the passivation layer and partially exposing the second source electrode, wherein the second conductive structure is further located in the sixth via hole.

12. A display panel, comprising the array substrate according to claim 1 .

13. A display device, comprising the display panel according to claim 12 .

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Cao Ke
• Yang Chengshao
• Wang Wenlong

Classifications

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F2201/121

  common or background · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G02F2201/123

  pixel · CPC title