Electrical mask validation

Patent metadata

Field	Value
Publication number	US-10650111-B2
Application number	US-201715827618-A
Country	US
Kind code	B2
Filing date	Nov 30, 2017
Priority date	Nov 30, 2017
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.

First claim

What is claimed is:

1. A method for ensuring semiconductor design integrity, the method comprising:
analyzing one or more photomask designs for one or more semiconductor chips, the photomask design having one or more circuit designs for one or more semiconductor chips and a kerf between the one or more circuit designs for the one or more semiconductor chips, the one or more circuit designs for the one or more semiconductor chips having a primary electrical design necessary for the operation of the one or more semiconductor chips, and white space within the primary electrical design, wherein the white space has no primary electrical design; and
inserting a secondary electrical circuit design into the white space of the one or more circuit designs for the one or more semiconductor chips, the secondary electrical circuit design having interconnects between at least two photomask layers, wherein the secondary electrical circuit design has one or more known testable electrical properties for validating the one or more semiconductor chips, and wherein the secondary electrical design is electrically isolated from the primary electrical design.

2. The method of claim 1 , further comprising:
building the one or more semiconductor chips according to the one or more photomask designs;
analyzing the one or more semiconductor chips for the one or more known electrical properties of the secondary electrical circuit design;
comparing the electrical properties of the one or more semiconductor chips to the one or more known electrical properties of the secondary electrical circuit design; and
validating the one or more semiconductor chips when the one or more known electrical properties of the secondary electrical circuit design match.

3. A method as in claim 2 , further comprising:
discarding the one or more semiconductor chips when the one or more known electrical properties of the secondary electrical circuit design do not match.

4. A method as in claim 1 , wherein the one or more known electrical properties is of at least one of the group consisting of: a design resistance, a design capacitance, and/or a design inductance.

5. A method as in claim 1 , wherein the secondary electrical circuit design comprises one or more photomask layers.

6. A method for ensuring semiconductor design integrity, the method comprising:
analyzing one or more photomask designs for one or more semiconductor chips, the photomask design having one or more circuit designs for one or more semiconductor chips and a kerf between the one or more circuit designs for the one or more semiconductor chips, the one or more circuit designs for the one or more semiconductor chips having a primary electrical design necessary for the operation of the one or more semiconductor chips, wherein the white space has no primary electrical design; and
inserting a secondary electrical circuit design into the white space of the one or more circuit designs for the one or more semiconductor chips, the secondary electrical circuit design having interconnects between at least two photomask designs, wherein the secondary electrical circuit design has one or more known electrical properties for validating the one or more semiconductor chips, and wherein the secondary electrical circuit design is electrically coupled to the primary electrical design.

7. A method as in claim 6 , further comprising:
building the one or more semiconductor chips according to the photomask design;
analyzing the one or more semiconductor chips for the one or more known electrical properties of the secondary electrical circuit design;
comparing the electrical properties of the one or more semiconductor chips to the one or more known electrical properties of the secondary electrical circuit design; and
validating the one or more semiconductor chips when the one or more known electrical properties of the secondary electrical circuit design match.

8. A method as in claim 7 , further comprising:
discarding the one or more semiconductor chips when the one or more known electrical properties of the secondary electrical circuit design do not match.

9. A method as in claim 6 , wherein the secondary electrical circuit design coupled to the primary electrical design is necessary for the operation of the one or more semiconductor chips.

10. A method as in claim 6 , wherein the one or more known electrical properties is of at least one of the group consisting of: a design resistance, a design capacitance, and/or a design inductance.

11. A method for ensuring semiconductor design integrity, the method comprising:
analyzing one or more photomask designs for one or more semiconductor chips, the photomask design having one or more circuit designs for one or more semiconductor chips and a kerf between the one or more circuit designs for the one or more semiconductor chips, the one or more circuit designs for the one or more semiconductor chips having a primary electrical design necessary for the operation of the one or more semiconductor chips, and white space within the primary electrical design, wherein the white space has no primary electrical design; and
inserting a secondary electrical circuit design into the white space of the one or more circuit designs for the one or more semiconductor chips, the secondary electrical circuit design having interconnects between at least two photomask designs, wherein the secondary electrical circuit design has one or more known electrical properties for validating the one or more semiconductor chips and wherein the secondary electrical circuit design comprises covershapes, the covershapes being areas of omitted electrical circuit design;
building the one or more semiconductor chips according to the photomask design;
analyzing the one or more semiconductor chips for the one or more known electrical properties of the secondary electrical circuit design;
comparing the electrical properties of the one or more semiconductor chips to the one or more known electrical properties of the secondary electrical circuit design; and
validating the one or more semiconductor chips when the one or more known electrical properties of the secondary electrical circuit design match.

12. A method as in claim 11 , wherein the secondary electrical circuit design is coupled to the primary electrical design and wherein the secondary electrical circuit design is necessary for the operation of the one or more semiconductor chips.

13. A method as in claim 11 , wherein the secondary electrical circuit design is electrically isolated from the primary electrical design.

14. A method as in claim 11 , wherein the one or more known electrical properties is of at least one of the group consisting of: a design resistance, a design capacitance, and/or a design inductance.

15. A method for ensuring semiconductor design integrity, the method comprising:
analyzing one or more photomask designs for a plurality of semiconductor chips, the photomask design having one or more circuit designs for one or more semiconductor chips and a kerf between the one or more circuit designs for the one or more semiconductor chips, the one or more circuit designs for the one or more semiconductor chips having a primary electrical design necessary for the operation of each one of the plurality semiconductor chips, and white space between the designs for the plurality of semiconductor chips, wherein the white space has no primary electrical design; and
inserting a secondary electrical circuit design into the white space of the one or more circuit designs for the plurality of semiconductor chips, the secondary electrical circuit des

Assignees

• IBM

Inventors

• Corliss Daniel
• Dunn Derren N
• Guillorn Michael A
• Fetterolf Shawn P

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F2117/06

  Spare resources, e.g. for permanent fault suppression · CPC title

• G06F2115/10

  Processors · CPC title

• G06F30/333 Primary

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title

• G06F30/30

  Circuit design · CPC title