Parameter correction for cascaded signal components

Patent metadata

Field	Value
Publication number	US-10645471-B2
Application number	US-201815955173-A
Country	US
Kind code	B2
Filing date	Apr 17, 2018
Priority date	Sep 27, 2016
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

Various examples are directed to systems and methods for providing correction to cascaded signal components. A correction signal may be applied to multiple signal components in a set of cascaded signal components.

First claim

The claimed invention is:

1. A cascaded signal component circuit, comprising:
a cascade of signal components comprising a first signal component and a second signal component, wherein the first signal component comprises a first switch set, wherein the first signal component draws more current through a first signal component positive side when the first switch set is in an on state than when the first switch set is in an off state, and wherein the second signal component comprises a second switch set having a first state that adds to a second signal component positive output;
a communications bus electrically coupled to a first signal component of the cascade of signal components and a second signal component of the cascade of signal components; and
a correction controller configured to perform operations comprising:
sending a first digital control signal to the first signal component on the communications bus, wherein at least a portion of the first digital control signal is provided to the first switch set; and
sending a second digital control signal to the second signal component on the communications bus, wherein at least a portion of the second digital control signal is provided to the second switch set.

2. The cascaded signal component circuit of claim 1 , wherein the communications bus comprises a data line, a clock line, and a write enable line, further comprising:
shifting a first set of bits corresponding to the first digital control signal on the data line to a first set of memory devices corresponding to the first signal component;
shifting a second set of bits corresponding to the second digital control signal on the data line to a second set of memory devices corresponding to the second signal component; and
cycling the write enable line.

3. The cascaded signal component circuit of claim 1 , wherein the first signal component comprises an amplifier, and wherein increasing current drawn through a first signal component positive side increases a gain of the amplifier.

4. The cascaded signal component circuit of claim 1 , wherein the first signal component comprises a buffer.

5. The cascaded signal component circuit of claim 4 , wherein the first switch set is coupled between a positive output of the first signal component and ground.

6. The cascaded signal component circuit of claim 1 , wherein the first signal component comprises a differential buffer, wherein the first signal component comprises a positive output and a negative output, wherein the differential buffer comprises a supplemental current source; and wherein the first switch set; when in the on state, enables the supplemental current source to increase current at the first signal component positive side.

7. The cascaded signal component circuit of claim 1 , further comprising:
a first data line;
a first set of memory elements electrically coupled in series on the first data line;
a second data line;
a second set of memory elements electrically coupled in series on the second data line; and
a multiplexer electrically coupled to the first set of memory elements and the second set of memory elements, wherein the correction controller is further configured to perform operations comprising:
serially transmit the first digital control signal to the first set of memory elements;
serially transmit the second digital control signal to the second set of memory elements; and
send to the multiplexer a select signal indicating the first digital control signal.

8. A method for operating a cascaded signal component circuit, comprising:
sending, by a correction controller of the cascaded signal component circuit, a first digital control signal to a first switch set associated with a first signal component of the cascaded signal component circuit;
shifting a first set of bits corresponding to the first digital control signal on a data line of a communications bus of the cascaded signal component circuit to first set of memory devices associated with the first signal component;
in response to the first digital control signal, assuming, by the first switch set, a first state that draws supplemental current through a first signal component positive side;
sending, by the correction controller, a second digital control signal to a second switch set associated with a second signal component of the cascaded signal component circuit;
shifting a second set of bits corresponding to the second digital control signal on the data line to a second set of memory devices corresponding to the second signal component;
cycling a write enable line of the communications bus to provide the first set of bits to the first switch set and the second set of bits to the second switch set; and
in response to the second digital control signal, assuming, by the second switch set, a second state that draws supplemental current through a second signal component positive side.

9. The method of claim 8 , wherein the first signal component comprises an amplifier, and wherein increasing current drawn through a first signal component positive side increases a gain of the amplifier.

10. The method of claim 8 , wherein the first signal component comprises a buffer, and wherein increasing current drawn through the first signal component positive side adjusts an inter symbol interference property of the buffer.

11. The method of claim 8 , wherein assuming the first state comprises generating an electrically conductive path between the first signal component positive side and ground.

12. The method of claim 8 , further comprising enabling a supplemental current source in response to the first switch set assuming the first state.

13. The cascaded signal component circuit of claim 1 , wherein the first switch set comprises a digital to analog converter (DAC).

14. The cascaded signal component circuit of claim 1 , wherein the first signal component comprises an amplifier having a gain, and wherein the first digital control signal affects the gain of the amplifier.

15. The cascaded signal component circuit of claim 1 , wherein the first signal component comprises a differential buffer, wherein a first signal output of the first signal component comprises a positive side output and a negative side output, wherein the differential buffer comprises a supplemental current source, and wherein the first switch set is configured to:
receive the first digital control signal; and
send, to the first signal component, at least one control signal to enable the supplemental current source to increase the positive side output.

16. The cascaded signal component circuit of claim 1 , wherein providing the first digital control signal to the first signal component comprises serially transmitting the first digital control signal to the first switch set via the communication bus.

17. A system for operating a cascaded signal component circuit, comprising:
means for sending a first digital control signal to a first switch set associated with a first signal component of the cascaded signal component circuit;
means for shifting a first set of bits corresponding to the first digital control signal on a data line of a communications bus of the cascaded signal component circuit to first set of memory devices associated with the first signal component;
means for causing the first switch set to, in response to the first digital control signal, assume a first state that draws supplemental current through a first signal component positive side;
means for sending a second digital control signal to a second switch set associated with a second signal component of th

Assignees

• Analog Devices Inc

Inventors

• St Germain Michael C
• Tam Kimo
• Ghaed Mohammad Hassan

Classifications

• H03M1/48

  Servo-type converters · CPC title

• G11C7/062

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• G11C8/06

  Address interface arrangements, e.g. address buffers · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/0617

  characterised by the use of methods or means not specific to a particular type of detrimental influence · CPC title