Parameter correction for cascaded signal components

Patent metadata

Field	Value
Publication number	US-9973833-B2
Application number	US-201615277739-A
Country	US
Kind code	B2
Filing date	Sep 27, 2016
Priority date	Sep 27, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

Various examples are directed to crosspoint switches and methods of use thereof. An example cross point switch comprises a first row buffer, a second row buffer, a first column buffer, and a second column buffer. The crosspoint switch may also comprise a first switch that, when closed, electrically couples the second row buffer to the first column buffer, and a correction controller. The correction controller may be configured to send a first correction signal to the first row buffer; send a second correction signal to the second row buffer; receive an indication that the first switch is closed; send a third correction signal to the first column buffer; and send a fourth correction signal to the second column buffer.

First claim

The claimed invention is:

1. A crosspoint switch, comprising:
a first row buffer comprising: a first row buffer input; a first row buffer output; and a first row buffer correction input;
a second row buffer comprising: a second row buffer input electrically coupled to the first row buffer output;
a second row buffer output; and a second row buffer correction input;
a first column buffer comprising: a first column buffer input; a first column buffer output; and a first column buffer correction input;
a second column buffer comprising: a second column buffer input electrically coupled to the first column buffer output; a second column buffer output; and a second column buffer correction input;
a first switch having an open position and a closed position, wherein when the first switch is in the closed position, the second row buffer output is electrically coupled to the first column buffer input;
a correction controller configured to:
send a first correction signal to the first row buffer;
send a second correction signal to the second row buffer;
receive an indication that the first switch is closed;
after receiving the indication that the first switch is closed, send a third correction signal to the first column buffer; and
after receiving the indication that the first switch is closed, send a fourth correction signal to the second column buffer.

2. The crosspoint switch of claim 1 , wherein the correction controller is further configured to:
send a first test signal to the first row buffer input;
while providing the first test signal to the first row buffer input, send a first plurality of test correction signals to the first row buffer;
select the first correction signal from the first plurality of test correction signals based at least in part on a first test output signal at the first row buffer output;
send a second test signal to the first row buffer input;
while providing the second test signal to the first row buffer input, send a second plurality of test correction signals to the second row buffer; and
select the second correction signal from the second plurality of test correction signals based at least in part on a second test output signal at the second row buffer output.

3. The crosspoint switch of claim 2 , further comprising a ring oscillator electrically coupled to the first row buffer input to generate the first test signal.

4. The crosspoint switch of claim 3 , further comprising:
a low pass filter electrically coupled to first row buffer output to generate a low-pass filtered output of the first row buffer;
a comparator electrically coupled to receive the low-pass filtered output of the first row buffer, wherein an output of the comparator is logical one if the low-pass filtered output of the first row buffer is greater than a threshold value;
a counter electrically coupled to receive the output of the comparator to sum the output of the comparator over a plurality of cycles of the comparator; and
a DAC electrically coupled to receive an output of the counter, convert the output of the counter to an analog signal, and provide the analog signal at the first row buffer input.

5. The crosspoint switch of claim 2 , wherein the correction controller is further configured to:
close the first switch;
send a third test signal to the first row buffer;
while providing the third test signal to the first row buffer, send a third plurality of test correction signals to the first column buffer; and
select the third correction signal from the third plurality of test correction signals based at least in part on a third test output signal at the first column buffer output while the third test signal is sent.

6. The crosspoint switch of claim 5 , further comprising:
a third row buffer comprising: a third row buffer input, a third row buffer output; and a third row buffer correction input;
a second switch having an open position and a closed position, wherein when the second switch is in the closed position, the third row buffer output is electrically coupled to the first column buffer input; and
wherein the correction controller is also configured to:
close the second switch;
send a fourth test signal to the third row buffer;
while sending the fourth test signal to the third row buffer, send a fourth plurality of test correction signals to the first column buffer correction input; and
select a fifth correction signal for the first column buffer from the fourth plurality of test correction signals.

7. The crosspoint switch of claim 6 , further comprising:
a first serial bus electrically coupling the correction controller to the first column buffer, wherein the first serial bus comprises a first data line; a second data line; and a map select line;
a first memory element on the first data line;
a second memory element on the second data line; and
a multiplexer on the map select line, wherein the multiplexer is electrically coupled to the first memory element and the second memory element, and wherein the correction controller is also configured to:
serially shift at least a portion of the third correction signal to the first memory element on the first data line;
serially shift at least a portion of the fifth correction signal to the second memory element on the second data line;
receive an indication that the first switch is to be closed; and
send to the multiplexer on the map selection line a first map selection signal instructing the multiplexer to connect the first memory element to the first column buffer.

8. The crosspoint switch of claim 1 , further comprising a first row buffer digital-to-analog converter (DAC) electrically coupled between the correction controller and the first row buffer correction input, the first row buffer DAC to:
receive the first correction signal;
convert the first correction signal to a first analog correction signal; and
send the first analog correction signal to the first row buffer correction input.

9. The crosspoint switch of claim 1 , wherein the first row buffer comprises:
a signal path comprising a positive side and a negative side; and
a correction unit comprising a supplemental positive side current source and a supplemental negative side current source, wherein the first correction signal enables at least one of the supplemental positive side current source or the supplemental negative side current source.

10. The crosspoint switch of claim 1 , further comprising:
a third column buffer comprising a third column buffer input; a third column buffer output electrically coupled to the first column buffer input; and a third column buffer correction input, wherein the correction controller is further configured to:
send a sixth correction signal to the third column buffer;
send a third test signal to the third column buffer input;
while providing the third test signal to the third column buffer input, send a fourth plurality of test correction signals to the first column buffer; and
select a seventh correction signal from the fourth plurality of test correction signals based at least in part on a fourth test output signal from the first column buffer while the third test signal is send.

11. A method for controlling a plurality of buffers, comprising:
sending a first correction signal to a first row buffer comprising a first row buffer output;
sending a second correction signal to a second row buffer comprising a second row buffer input electrically coupled to the first row buffer output;
receiving an indication that a first switch is to be closed, wherein the first switch has an open position and a closed position, and wherein when the first switch is in the closed position, a sec

Assignees

• Analog Devices Inc

Inventors

• St Germain Michael C
• Tam Kimo
• Ghaed Mohammad Hassan

Classifications

• H03M1/48

  Servo-type converters · CPC title

• H04N21/60

  Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client {, e.g. sending from server to client commands for recording incoming content stream}; Communication details between server and client · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C8/06

  Address interface arrangements, e.g. address buffers · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title