Soft error-resilient latch

Patent metadata

Field	Value
Publication number	US-10644700-B2
Application number	US-201916452051-A
Country	US
Kind code	B2
Filing date	Jun 25, 2019
Priority date	Jun 27, 2018
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

A latch is provided. The latch includes a plurality of storage nodes including a plurality of data storage nodes configured to store a data bit having one of two states and a plurality of complementary data storage nodes configured to store a complement of the data bit. The latch includes a plurality of supply voltage multi-dependency stages respectively corresponding to the plurality of storage nodes. Each supply voltage multi-dependency stage has an output coupled to a storage node and at least two control inputs respectively coupled to at least two other storage nodes of the plurality of storage nodes. The supply voltage multi-dependency stage is configured to cause a state of the data bit stored in the storage node to change from a first state to a second state in response a change in both states of two data bits respectively stored in the at least two other storage nodes.

First claim

The invention claimed is:

1. A circuit, comprising:
a first latch including:
a plurality of storage nodes including:
a plurality of data storage nodes each configured to store a data bit having one of two states including a first state and a second state; and
a plurality of complementary data storage nodes each configured to store a complement of the data bit;

a plurality of first voltage multi-dependency stages respectively corresponding to the plurality of storage nodes, each first voltage multi-dependency stage having an output coupled to a respective storage node of the plurality of storage nodes and at least two control inputs respectively coupled to at least two other storage nodes of the plurality of storage nodes, the first voltage multi-dependency stage configured to cause the state of the data bit stored in the storage node to change from the second state to the first state in response to a change in both states of two data bits respectively stored in the at least two other storage nodes; and
a plurality of second voltage multi-dependency stages respectively corresponding to the plurality of storage nodes, each second voltage multi-dependency stage having an output coupled to the respective storage node of the plurality of storage nodes and at least two control inputs respectively coupled to the at least two other storage nodes of the plurality of storage nodes, the second voltage multi-dependency stage configured to cause the state of the data bit stored in the storage node to change from the first state to the second state in response to a change in both states of two data bits respectively stored in the at least two other storage nodes.

2. The circuit of claim 1 , wherein the second voltage multi-dependency stage comprises:
a first transistor having a first conduction terminal coupled to the storage node, a control terminal coupled to a first storage node of the at least two other storage nodes and a second conduction terminal; and
a second transistor having a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conduction terminal coupled to a second voltage node that supplies a second voltage and a control terminal coupled to a second storage node of the at least two other storage nodes.

3. The circuit of claim 1 , wherein the first voltage multi-dependency stage is configured to refrain from causing the state of the data bit stored in the storage node to change from the second state to the first state when only one of the two data bits respectively stored in the at least two other storage nodes changes states or when neither one of the two data bits respectively stored in the at least two other storage nodes changes states.

4. The circuit of claim 1 , wherein the first voltage multi-dependency stage comprises:
a first transistor having a first conduction terminal coupled to the storage node, a control terminal coupled to a first storage node of the at least two other storage nodes and a second conduction terminal; and
a second transistor having a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conduction terminal coupled to a first voltage node that supplies a first voltage and a control terminal coupled to a second storage node of the at least two other storage nodes.

5. The circuit of claim 1 , wherein the first latch includes:
a first input stage coupled to the plurality of storage nodes and configured to:
receive a clock signal having one of two clock states including a first clock state and a second clock state;
receive a data signal having a data signal state;
in response to the clock signal having the first clock state, set the data bit and the complement of the data bit based on the data signal state; and
in response to the clock signal having the second clock state, refrain from setting the data bit and the complement of the data bit.

6. The circuit of claim 5 , comprising:
a second latch coupled to the first latch and including a plurality of second latch storage nodes, the second latch being configured to:
receive the clock signal; and
in response to the clock signal having the second clock state, cause data stored in the plurality of storage nodes to be transferred to the plurality of second latch storage nodes, respectively.

7. A method, comprising:
storing a plurality of data bits in a respective plurality of storage nodes of a latch, each data bit of the plurality of data bits being stored in a respective storage node of the plurality of storage nodes;
determining, by a first multi-dependency stage having an output coupled to the storage node of the plurality of storage nodes and two inputs respectively coupled to at least two other storage nodes of the plurality of storage nodes, whether two respective states of two data bits stored in the at least two other storage nodes, respectively, changed;
in response to determining that the two respective states changed, causing a state of a data bit stored in the storage node to change, wherein causing the state of the data bit stored in the storage node to change includes causing the state of the data bit to change from a first state to a second state, and wherein each data bit of the plurality of data bits has one of two states including the first state corresponding to a reference voltage and a second state corresponding to a supply voltage;
in response to determining that one of the two respective states or none of the two respective states changed, refraining from causing the state of the data bit stored in the storage node to change;
determining, by a second multi-dependency stage having an output coupled to the storage node of the plurality of storage nodes and two inputs respectively coupled to the at least two other storage nodes of the plurality of storage nodes, whether the two respective states of the two data bits stored in the at least two other storage nodes, respectively, changed from the first state to the second state; and
in response to determining that the two respective states changed from the first state to the second state, causing the state of the data bit stored in the storage node to change from the second state to the first state.

8. The method of claim 7 , wherein the first multi-dependency stage includes:
a first transistor having a first conduction terminal coupled to the storage node, a control terminal coupled to a first storage node of the at least two other storage nodes and a second conduction terminal; and
a second transistor having a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conduction terminal coupled to a supply voltage node that supplies the supply voltage and a control terminal coupled to a second storage node of the at least two other storage nodes.

9. The method of claim 8 , wherein the second multi-dependency stage includes:
a first transistor having a first conduction terminal coupled to the storage node, a control terminal coupled to the first storage node of the at least two other storage nodes and a second conduction terminal; and
a second transistor having a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conduction terminal coupled to a supply voltage node that supplies the supply voltage and a control terminal coupled to the second storage node of the at least two other storage nodes.

10. A latch, comprising:
a supply voltage node;
a reference voltage node;
a plurality of storage nodes including a first, second and third storage nodes; and
a plurality of supply voltage multi-dependency stages including a first supply voltage multi-dependency

Assignees

• St Microelectronics Int Nv
• St Microelectronics Srl

Inventors

• Veggetti Andrea Mario
• Jain Abhishek

Classifications

• G11C29/74

  using duplex memories, i.e. using dual copies · CPC title

• G11C29/816

  for an application-specific layout · CPC title

• G01R31/31816

  Soft error testing; Soft error rate evaluation; Single event testing · CPC title

• H03K3/356121

  with synchronous operation (H03K3/35613, H03K3/356147 take precedence) · CPC title

• H03K3/013

  Modifications of generator to prevent operation by noise or interference · CPC title