Dual interlocked storage cell (DICE) latch sharing active region with neighbor DICE latch and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-10014048-B2
Application number	US-201715486051-A
Country	US
Kind code	B2
Filing date	Apr 12, 2017
Priority date	Nov 8, 2016
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

A dual interlocked storage cell (DICE) latch may be provided. A semiconductor device may be provided. The semiconductor device may include a DICE latch.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first dual interlocked storage cell (DICE) latch; and
a second DICE latch located adjacent to the first DICE latch, and configured to share a specific region thereof with the first DICE latch,
wherein each of the first DICE latch and the second DICE latch has at least 4 nodes storing at least 2 pairs of complementary values.

2. The semiconductor device according to claim 1 , wherein:
each of the first DICE latch and the second DICE latch is configured in a manner that transistors receiving data are formed in different active regions.

3. The semiconductor device according to claim 1 , wherein the first DICE latch and the second DICE latch are configured to share an active region of any one of transistors receiving data.

4. The semiconductor device according to claim 3 , wherein the first DICE latch and the second DICE latch are configured to share an active region of one of the outermost transistors from among the transistors receiving data.

5. The semiconductor device according to claim 4 , wherein the first DICE latch and the second DICE latch are arranged symmetrical to each other on the basis of the shared active region.

6. The semiconductor device according to claim 1 , wherein each of the first DICE latch and the second DICE latch includes:
a latch circuit configured to store data through at least four even connection lines which are alternately inversion-driven; and
a data input circuit configured to input data to the latch circuit based on an input control signal.

7. The semiconductor device according to claim 6 , wherein the data input circuit includes:
a first switching element configured to couple a first data input terminal receiving data of a first logic level to a first connection line based on the input control signal;
a second switching element configured to couple a second data input terminal receiving data of a second logic level opposite to the first logic level to a second connection line based on the input control signal;
a third switching element configured to couple the first data input terminal to a third connection line based on the input control signal; and
a fourth switching element configured to couple the second data input terminal to a fourth connection line based on the input control signal.

8. The semiconductor device according to claim 7 , wherein:
in each of the first DICE latch and the second DICE latch, the first to fourth switching elements are formed in different active regions.

9. The semiconductor device according to claim 7 , wherein the first switching element of the first DICE latch and the first switching element of the second DICE latch are configured to share an active region.

10. The semiconductor device according to claim 7 , wherein the first to fourth switching elements of the first DICE latch are arranged symmetrical to the first to fourth switching elements of the second DICE latch on the basis of a shared active region.

11. The semiconductor device according to claim 6 , further comprising:
a reset circuit configured to couple connection lines having the same logic level from among the connection lines to a power-supply voltage terminal.

12. A dual interlocked storage cell (DICE) latch comprising:
a DICE latch region including:
latch circuits configured to receive data; and
a data input circuit including a plurality of transistors configured to input the data to a corresponding latch circuit based on an input control signal,
wherein an active region of one of the transistors from the plurality of transistors is formed to deviate from the DICE latch region to share with one of the transistors of a contiguous DICE latch,
wherein the DICE latch region includes at least 4 nodes storing at least 2 pairs of complementary values.

13. The DICE latch according to claim 12 , wherein the one of the transistors formed to deviate from the DICE latch region is an outermost transistor from among the plurality of transistors.

14. The DICE latch according to claim 12 , wherein the active regions of the plurality of transistors are separated from each other.

Assignees

• Sk Hynix Inc

Inventors

• Ko Dong Uc

Classifications

• H10W20/427 Primary

  Power or ground buses · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H01L27/0207

  Electricity · mapped topic

• H01L27/0705

  Electricity · mapped topic

• G11C11/417

  for memory cells of the field-effect type · CPC title