Tunable gain amplifier

Patent metadata

Field	Value
Publication number	US-10644662-B2
Application number	US-201715825400-A
Country	US
Kind code	B2
Filing date	Nov 29, 2017
Priority date	Nov 29, 2017
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

A amplifier circuit in some embodiment includes a differential amplifier have a pair of current sources. Each of the current sources includes two or more current-generating transistors and respective switching transistors, which can be turned on and off by a gain input code to tune the gain of the amplifier. A common-mode controller includes a similar pair of current sources as the differential amplifier. The common mode controller receives a common-mode signal of the input signal and a common-mode gain input code, and maintains the common-mode gain of the amplifier circuit when the differential gain changes. The amplifier circuit is switchable between a buffer mode and an equalizer mode.

First claim

What is claimed is:

1. A circuit, comprising:
a differential amplifier adapted to receive a pair of input signals at an input of a respective pair of input terminals and provide at a first output a differential output signal representing a gain of the difference between the pair of input signals, the differential amplifier having a gain input terminal and being adapted to set the gain in response to a gain input at the gain input terminal; and
a common-mode controller adapted to receive a signal corresponding to a common-mode signal of the pair of input signals and having a second output connected to the first output, the common-mode controller having a common-mode gain input terminal and being adapted to set a common-mode gain of the circuit in response to a common-mode gain input at the common-mode gain input terminal.

2. The circuit of claim 1 , wherein the common-mode controller is adapted to maintain a common-mode gain for different values of the gain of the differential amplifier.

3. The circuit of claim 1 , wherein the common-mode controller is adapted to maintain a common-mode gain in response to a common-mode gain input that is correlated to the gain input of the differential amplifier.

4. The circuit of claim 1 , wherein the gain input of the differential amplifier and common-mode gain input are digital inputs and are complements of each other.

5. The circuit of claim 1 , wherein the differential amplifier is switchable between a buffer mode and an equalizer mode.

6. The circuit of claim 5 , wherein the first output comprises a pair of output terminals, and the differential amplifier comprises a first and second input-bias circuits, each comprising:
a first plurality of transistors, each having a control electrode, a first main electrode, and a second main electrode, the control electrodes being connected to each other and to a respective one of the input terminals, the first main electrodes being connected to each other and to a respective one of the pair of output terminal; and
a first plurality of current sources, each connected between the second main electrode of a respective one of the first plurality of transistors and a first voltage supply;
the differential amplifier further comprising:
a first and second load, each connected between a second voltage supply and the first main electrodes of the first plurality of transistors of a respective one of the input-bias circuits.

7. The circuit of claim 6 , wherein the differential amplifier further comprises a plurality of connecting elements alternately connectable between the first and second current sources, a first one of the plurality of connecting elements being adapted to, when connected between the first and second current sources, place the differential amplifier in a buffer mode, and a second one of the plurality of connecting elements being adapted to, when connected between the first and second current sources, place the differential amplifier in an equalizer mode.

8. The circuit of claim 7 , wherein the first one of the plurality of connecting elements is substantially purely resistive, and the second one of the plurality of connecting elements has a frequency-dependent gain.

9. The circuit of claim 6 , wherein the common-mode controller comprise a first and second branch circuits, each comprising:
a second plurality of transistors, each having a control electrode, a first main electrode, and a second main electrode, the control electrodes of the second plurality of transistors adapted to receive a signal corresponding to the common-mode signal of the input signals, the first main electrodes adapted to receive the output signal from a respective one of the input-bias circuits; and
a second plurality of current sources, each connected between the second main electrode of a respective one of the second plurality of transistors and the first voltage supply, the second plurality of current sources being adapted to provide a variable current through the respective branch circuit.

10. The circuit of claim 9 , wherein each of the current sources in the differential amplifier and common-mode controller comprises:
a current generating transistor having a control electrode, a first main electrode and a second electrode, the second electrode being connected to the first voltage supply, the control electrode being adapted to receive a bias signal; and
a switching transistor having a control electrode, first main electrode and a second electrode, wherein
in the differential amplifier, the control electrode of the of the switching transistor is adapted to receive at least a part of the gain input, and the switching transistor is adapted to open and close a connection between the second main electrode of a respective one of the first plurality of the transistors and the first main electrode of the current generating transistor, and
in the common-mode controller, the control electrode of the of the switching transistor is adapted to receive at least a part of the common-mode gain input, and the switching transistor is adapted to open and close a connection between the second main electrode of a respective one of the second plurality of the transistors and the first main electrode of the current generating transistor.

11. The circuit of claim 1 , wherein the differential amplifier has a variable gain and is without a degeneration resistor.

12. The circuit of claim 10 , wherein, within each of the first and second plurality of current sources, one of the plurality of current-generating transistors is adapted to generate through the first electrode a current that is multiple times of a current generated through the first electrode of another one of the plurality of current-generating transistors.

13. A circuit, comprising:
a differential amplifier, comprising:
a first pair of transistors, each having a control electrode adapted to receive a respective input signal; a first main electrode adapted to provide an output signal; and a second main electrode;
a pair of loads, each connected between the first main electrode of a respective one of the pair of transistors and a first voltage supply; and
a pair of current sources, each connected between the second main electrode of a respective one of the pair of transistors and a second voltage supply, and adapted to output a current of a variable magnitude,
the differential amplifier being switchable between a buffer mode and an equalizer mode,
wherein the differential amplifier comprises a plurality of connecting elements alternately connectable between the pair of current sources, a first one of the plurality of connecting elements being adapted to, when connected between the pair of current sources, place the differential amplifier in a buffer mode, and a second one of the plurality of connecting elements being adapted to, when connected between the pair of current sources, place the differential amplifier in an equalizer mode.

14. The circuit of claim 13 , wherein the first one of the plurality of connecting elements is substantially purely resistive, and the second one of the plurality of connecting elements has a frequency-dependent gain.

15. The circuit of claim 13 , further comprising a common-mode controller, comprising:
a second pair of transistors, each having a control electrode; a first main electrode adapted to receive a respective one of the output signals; and a second main electrode, the control electrodes of the second pair of transistors adapted to receive a signal corresponding to a common-mode signal of the input signals; and
a pair of current sources, each connected between the second m

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Shu-Chun
• Chen Wei Chih
• Shih Yu-Nan

Classifications

• H03F3/45632

  in differential amplifiers with FET transistors as the active amplifying circuit (H03F3/4578 takes precedence) · CPC title

• H03F3/45076 Primary

  characterised by the way of implementation of the active amplifying circuit in the differential amplifier · CPC title

• H03F2203/45702

  the LC comprising two resistors · CPC title

• H03F3/45197

  Pl types (H03F3/45224, H03F3/45251 take precedence) · CPC title

• H03F3/45179 Primary

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title