Combined CMP and RIE contact scheme for MRAM applications

Patent metadata

Field	Value
Publication number	US-10644233-B2
Application number	US-201815961221-A
Country	US
Kind code	B2
Filing date	Apr 24, 2018
Priority date	Mar 1, 2017
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

A method is presented for establishing a top contact to a magnetic tunnel junction (MTJ) device, the method including selectively etching, via a first etching process, an oxide layer to expose a top surface of a nitride layer of a dummy fill shape and selectively etching, via a second etching process, a top portion of the nitride layer of the dummy fill shape to expose a top surface thereof. The method further includes selectively etching, via the second etching process, the oxide layer to expose a top surface of a nitride layer of the MTJ device, and selectively etching, via the first etching process, a top portion of the nitride layer of the MTJ device to expose a top surface thereof such that a height of the MTJ device is approximately equal to a height of the dummy fill shape.

First claim

What is claimed is:

1. A semiconductor structure for establishing a top contact to a first device, the structure comprising: the first device; a second device, the first and second devices planarized by alternating a first etch process and a second etch process based on a predetermined height offset between the first and second devices such that the first and second devices are uniformly contacted across a wafer, and a U-shaped dielectric layer separating the first device from the second device, the U-shaped dielectric layer positioned, in its entirety, directly between the first and second devices, wherein the first device is a magnetic tunnel junction (MTJ) device and the second device is a dummy fill shape.

2. The structure of claim 1 , wherein the first etch process is a chemical-mechanical planarization (CMP) process and the second etch process is a reactive ion etch (RIE) process.

3. The structure of claim 1 , wherein the U-shaped dielectric layer directly contacts both the first and second devices.

4. The structure of claim 1 , wherein the uniform top contact across the wafer is defined without exposure to reactive plasma chemistries.

5. The structure of claim 1 , wherein alternating the first etch process and the second etch process involves a first dielectric layer selectively etched by the first etch process to expose a top surface of a second dielectric layer of the second device.

6. The structure of claim 5 , wherein alternating the first etch process and the second etch process further involves a top portion of the second dielectric layer of the second device selectively etched by the second etch process to expose a top surface thereof.

7. The structure of claim 6 , wherein alternating the first etch process and the second etch process further involves the first dielectric layer selectively etched by the second etch process to expose a top surface of a third dielectric layer of the first device.

8. The structure of claim 7 , wherein alternating the first etch process and the second etch process further involves a top portion of the third dielectric layer of the first device selectively etched by the first etch process to expose a top surface thereof.

9. The structure of claim 8 , wherein alternating the first etch process and the second etch process results in a height of the first device being approximately equal to a height of the second device.

10. A structure for establishing a top contact for a plurality of magnetic tunnel junction (MTJ) devices by planarizing the MTJ devices by alternating first and second etch processes, the structure comprising: a stack of conducting layers; a first device and a second device both horizontally misaligned with respect to the stack of conducting layers; a first dielectric layer disposed over the stack of conducting layers; a second dielectric layer disposed over the first dielectric layer; trenches extending within the first and second dielectric layers; and a conducting material disposed within the trenches, wherein the first device is a magnetic tunnel junction (MTJ) device and the second device is a dummy fill shape.

11. The structure of claim 10 , wherein the first etch process is a chemical-mechanical planarization (CMP) process and the second etch process is a reactive ion etch (RIE) process.

12. The structure of claim 11 , wherein the stack of conducting layers includes a first layer, a second layer, and a third layer.

13. The structure of claim 12 , wherein the first layer is a first tantalum nitride (TaN) layer, the second layer is a ruthenium (Ru) layer, and the third layer is a second tantalum nitride (TaN) layer.

14. The structure of claim 13 , wherein the first and second TaN layers have a thickness of about 5 nm.

15. The structure of claim 13 , wherein a thickness of the Ru layer is about 20 nm.

16. The structure of claim 10 , wherein the conducting material is copper (Cu).

17. The structure of claim 16 , wherein the Cu contacts a top surface of the stack of conducting layers to create metal trench Cu lines over the plurality of MTJ devices.

18. The structure of claim 17 , wherein the plurality of MTJs devices are substantially aligned with the conducting material.

Assignees

• IBM

Inventors

• Lofaro Michael F
• Marchack Nathan P
• Nowak Janusz J
• O'Sullivan Eugene J

Classifications

• H01L43/12 Primary

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic

• H10N50/80

  Constructional details · CPC title