Techniques for contact formation in self-aligned replacement gate device

Patent metadata

Field	Value
Publication number	US-10644117-B2
Application number	US-201815977324-A
Country	US
Kind code	B2
Filing date	May 11, 2018
Priority date	May 11, 2018
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

A method may include providing a device structure, where the device structure includes a semiconductor region, and a gate structure, disposed over the semiconductor region. The gate structure may further include a gate metal. The method may further include oxidizing an upper portion of the gate metal, wherein the upper portion forms an oxide cap, and wherein a lower portion of the gate metal remains metallic.

First claim

What is claimed is:

1. A method, comprising:
providing a device structure, the device structure comprising:
a semiconductor region, and
a gate structure, disposed over the semiconductor region, the gate structure comprising a gate metal; and

oxidizing an upper portion of the gate metal, wherein the upper portion forms an oxide cap, and wherein a lower portion of the gate metal remains metallic,
wherein the gate structure comprises a tungsten gate metal, a nitride sidewall spacer, disposed along the tungsten gate metal, and wherein the device structure further comprises a dielectric, disposed outside the nitride sidewall spacer, the method further comprising:
selectively etching a top region of the oxide cap, wherein a bottom region of the oxide cap remains above the lower portion of the gate metal after the selectively etching.

2. The method of claim 1 , the oxidizing comprising performing a plasma oxidation.

3. The method of claim 2 , wherein the plasma oxidation comprises generating oxygen ions and directing the oxygen ions to the device structure at an ion energy of 500 eV to 10 keV.

4. The method of claim 1 , further comprising forming a source/drain contact to the semiconductor region.

5. The method of claim 1 , wherein the selectively etching the top region of the oxide cap comprises planarizing the upper portion.

6. A method, comprising:
forming a device structure, the device structure comprising:
a semiconductor fin;
a gate structure, disposed over a first portion of the semiconductor fin, the gate structure comprising a gate metal and a set of sidewall spacers; and
a source/drain structure, disposed over a second portion of the semiconductor fin;

oxidizing an upper portion of the gate metal, wherein the upper portion forms an oxide cap, and wherein a lower portion of the gate metal remains metallic; and
selectively removing a top region of the oxide cap, wherein a bottom region of the oxide cap remains above the lower portion of the gate metal.

7. The method of claim 6 , the gate metal comprising tungsten.

8. The method of claim 6 , the forming the device structure comprising:
forming a dummy gate structure, the dummy gate structure comprising a sacrificial gate material and the set of sidewall spacers;
selectively removing the sacrificial gate material; and
replacing the sacrificial gate material with a gate metal, wherein the gate metal extends above the set of sidewall spacers; and
polishing the gate metal to remove a portion of the gate metal extending above the set of sidewall spacers.

9. The method of claim 6 , the oxidizing comprising performing a plasma oxidation.

10. The method of claim 9 , wherein the plasma oxidation comprises generating oxygen ions and directing the oxygen ions to the device structure at an ion energy of 500 eV to 10000 eV.

11. The method of claim 6 , wherein the oxide cap extends above the set of sidewall spacers after the oxidizing, and wherein the selectively removing the top region comprises planarizing the oxide cap with respect to the set of sidewall spacers.

12. The method of claim 6 , wherein the gate structure comprises a tungsten gate metal, a nitride sidewall spacer, disposed along the tungsten gate metal, and wherein the device structure further comprises a dielectric, disposed outside the nitride sidewall spacer, wherein the oxide cap comprises a tungsten oxide, wherein the selectively removing the oxide comprises selectively etching the tungsten oxide with respect to the nitride sidewall spacer and the dielectric.

13. A method, comprising:
providing a device structure, the device structure comprising:
a semiconductor fin, and
a gate structure, disposed over the semiconductor fin, the gate structure comprising a tungsten gate metal and a set of sidewall spacers;

oxidizing an upper portion of the tungsten gate metal, wherein the upper portion forms a tungsten oxide, and wherein a lower portion of the tungsten gate metal remains metallic; and
selectively removing a top region of the tungsten oxide, wherein a bottom region of the tungsten oxide remains above the lower portion of the tungsten gate metal.

14. The method of claim 13 , wherein the tungsten oxide extends above the set of sidewall spacers after the oxidizing, and wherein the selectively removing the top region comprises planarizing the oxide with respect to the set of sidewall spacers.

15. The method of claim 13 , wherein the gate structure comprises a nitride sidewall spacer, disposed along the tungsten gate metal, and wherein the device structure further comprises a dielectric, disposed outside the nitride sidewall spacer, wherein the selectively removing the top region of the tungsten oxide comprises selectively etching the tungsten oxide with respect to the nitride sidewall spacer and the dielectric.

Assignees

• Varian Semiconductor Equipment Ass Inc

Inventors

• Sung Min Gyu
• Wang Wenhui
• Lee Jun
• Varghese Sony

Classifications

• H01L29/66545

  Electricity · mapped topic

• H01L21/32115

  Electricity · mapped topic

• H01L29/401 Primary

  Electricity · mapped topic

• H01L29/495

  Electricity · mapped topic

• H01L21/28247

  Electricity · mapped topic