Dual-gate PMOS field effect transistor with InGaAs channel

Patent metadata

Field	Value
Publication number	US-10644100-B2
Application number	US-201615539478-A
Country	US
Kind code	B2
Filing date	Dec 28, 2016
Priority date	Oct 12, 2016
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

The present disclosure relates to the field of semiconductor Integrated Circuit (IC) manufacture, and provides an InGaAs-based double-gate PMOS Field Effect Transistor (FET). The FET includes a bottom gate electrode, a bottom gate dielectric layer, a bottom gate interface control layer, an InGaAs channel layer, an upper interface control layer, a highly doped P-type GaAs layer, an ohmic contact layer, source/drain metal electrodes, a top gate dielectric layer and a top gate electrode. The source/drain metal electrodes are located on opposite sides of the ohmic contact layer. A gate trench structure is etched to an upper surface of the interface control layer between the source and drain metal electrodes. The top gate dielectric layer uniformly covers an inner surface of the gate trench structure, and the top gate electrode is provided on the top gate dielectric layer. The present disclosure provides a PMOS FET with better gate control functionality and a low interface density with the double-gate structure and interface control layer design, in order to meet the requirements of high-performance PMOS transistors.

First claim

We claim:

1. A Field Effect Transistor (FET), comprising:
a bottom gate structure comprising a bottom gate electrode and a bottom gate dielectric layer;
an InGaAs channel layer;
a top gate structure comprising a top gate electrode and a top gate dielectric layer different from the bottom gate electrode and bottom gate dielectric layer; and
a lower interface control layer and an upper interface control layer,
wherein the bottom gate dielectric layer is disposed between the bottom gate electrode and the InGaAs channel layer, and the top gate dielectric layer is disposed between the top gate electrode and the InGaAs channel layer,
wherein the lower interface control layer is disposed between the bottom gate dielectric layer and the InGaAs channel layer, and the upper interface control layer is disposed between the top gate structure and the InGaAs channel layer, and
wherein the upper interface control layer and the lower interface control layer each have a bandgap greater than that of the InGaAs channel layer, and the upper interface control layer and the lower interface control layer each has a first type of quantum well band alignment relationship with the InGaAs channel layer, and
wherein the upper interface control layer and the lower interface control layer each have a thickness in a range between a single atomic layer and 20 nm.

2. The FET according to claim 1 , wherein the InGaAs channel layer has a thickness of 1 to 20 nm, with a low In composition between 0.2 and 0.4.

3. The FET according to claim 1 , wherein holes in the InGaAs channel layer have a quantum confinement effect.

4. The FET according to claim 1 , wherein the bottom gate electrode comprises an electrode metal layer and a work function layer.

5. The FET according to claim 1 , further comprising:
highly doped P-type GaAs layers disposed on the upper interface control layer on opposite sides of the top gate structure, respectively,
ohmic contact layers disposed on the highly doped P-type GaAs layers, respectively, and source/drain metal electrodes disposed on the ohmic contact layers, respectively.

6. The FET according to claim 5 , wherein each of the ohmic contact layer comprises a heavily doped InGaAs material with a doping concentration greater than 1e 19 cm −3 .

7. The FET according to claim 5 , wherein each of the highly doped P-type GaAs layer has a doping concentration greater than 1e 18 cm −3 .

8. The FET according to claim 5 , wherein each of the upper interface control layer and the lower interface control layer has a lattice having a matching or pseudo-mating relationship with that of the InGaAs channel layer.

9. The FET according to claim 5 , wherein the top gate dielectric layer uniformly extends on a surface of the upper interface control layer between the highly doped P-type GaAs layers opposite to each other, surfaces of the highly doped P-type GaAs layers facing each other, and surfaces of the ohmic contact layers facing each other.

10. The FET according to claim 1 , wherein the top gate electrode comprises an electrode metal layer and a work function layer.

11. The FET according to claim 1 , wherein the top gate dielectric layer and the bottom gate dielectric layer each have a dielectric constant K greater than 8.

12. The FET according to claim 11 , wherein the top gate dielectric layer and the bottom gate dielectric layer each comprises a material selected from oxide, nitride, oxynitride, any mixture thereof, or any combination of multiple layers thereof.

13. A Field Effect Transistor (FET), comprising:
a bottom gate structure comprising a bottom gate electrode and a bottom gate dielectric layer;
an InGaAs channel layer having a thickness of 1 to 20 nm,
a top gate structure comprising a top gate electrode and top gate dielectric layer, wherein the top gate electrode and top gate dielectric layer are different from the bottom gate electrode and bottom gate dielectric layer; and
a lower interface control layer and an upper interface control layer wherein the upper interface control layer and the lower interface control layer each have a thickness in a range between a single atomic layer and 20 nm and wherein the upper interface control layer and the lower interface control layer both have a lattice having a matching or pseudo-mating relationship with that of the InGaAs channel layer,
wherein the bottom gate dielectric layer is disposed between the bottom gate electrode and the InGaAs channel layer, and the top gate dielectric layer is disposed between the top gate electrode and the InGaAs channel layer,
wherein the lower interface control layer is disposed between the bottom gate dielectric layer and the InGaAs channel layer, and the upper interface control layer is disposed between the top gate dielectric layer and the InGaAs channel layer, and
wherein the upper interface control layer and the lower interface control layer each have a bandgap greater than that of the InGaAs channel layer, and the upper interface control layer and the lower interface control layer each has a first type of quantum well band alignment relationship with the InGaAs channel layer.

Assignees

• Inst Of Microelectronics Cas

Inventors

• Wang Shengkai
• Liu Honggang
• Sun Bing
• Chang Hudong

Classifications

• H01L29/66666

  Electricity · mapped topic

• H01L29/205

  Electricity · mapped topic

• H01L29/66484

  Electricity · mapped topic

• H01L29/7832

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic