Method of manufacturing damascene thin-film resistor (TFR) in poly-metal dielectric

Patent metadata

Field	Value
Publication number	US-10643887-B2
Application number	US-201816037941-A
Country	US
Kind code	B2
Filing date	Jul 17, 2018
Priority date	Oct 6, 2017
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

A damascene thin-film resistor (TFR), e.g., a damascene thin-film resistor module formed within a poly-metal dielectric (PMD) layer using a single added mask layer, and a method for manufacturing such a device, are disclosed. A method for manufacturing a TFR structure may include forming a pair of spaced-apart TFR heads formed as self-aligned silicide poly (salicide) structures, depositing a dielectric layer over the salicide TFR heads, patterning and etching a trench extending laterally over at least a portion of each salicide TFR head and exposing a surface of each salicide TFR heads is exposed, and depositing a TFR material into the trench and onto the exposed TFR head surfaces, to thereby form a TFR layer that bridges the pair of spaced-apart TFR heads.

First claim

The invention claimed is:

1. A method for manufacturing a thin film resistor (TFR) structure, the method comprising:
forming a pair of TFR heads spaced apart from each other, each TFR head comprising a self-aligned silicide (salicide) structure;
depositing a dielectric layer over the salicide TFR heads;
patterning a photoresist trench into a photoresist layer using photo lithography, the patterned photoresist trench extending laterally over at least a portion of each salicide TFR head;
etching through the photoresist trench and through at least a portion of the dielectric layer and stopping at the salicide TFR heads to define a single TFR trench, such that a surface of each salicide TFR head is exposed in the single TFR trench; and
depositing a TFR material into the single TFR trench and onto the exposed surfaces of the salicide TFR heads, to thereby form a TFR layer that bridges the pair of spaced-apart salicide TFR heads.

2. The method of claim 1 , wherein the TFR material comprises SiCr.

3. The method of claim 1 , comprising annealing the TFR structure after depositing the TFR material to alter a temperature coefficient of resistance (TCR) of the TFR material.

4. The method of claim 3 , comprising annealing the structure to achieve a TCR of the TFR material to a non-zero TCR value of less than |100 ppm/° C.|.

5. The method of claim 3 , comprising annealing the structure to achieve a TCR of the TFR material to a non-zero TCR value of less than |50 ppm/° C.|.

6. The method of claim 3 , comprising annealing the structure to achieve a TCR of the TFR material to a non-zero TCR value of less than |10 ppm/° C.|.

7. The method of claim 3 , comprising annealing the structure at a temperature in the range of 450° C. to 550° C.

8. The method of claim 1 , further comprising performing a Chemical Mechanical Polishing (CMP) process to remove portions of the TFR material outside the single TFR trench.

9. The method of claim 8 , further comprising, after the removal process to remove portions of the TFR material outside the single TFR trench, forming at least one of a phosphosilicate glass (PSG) layer or an un-doped silicate glass (USG) cap oxide layer over the structure.

10. The method of claim 1 , further comprising forming conductive contacts to contact each salicide TFR head.

11. The method of claim 1 , further comprising conductively connecting the TFR structure to at least one aluminum interconnect.

12. The method of claim 1 , further comprising conductively connecting the TFR structure to at least one copper interconnect.

13. The method of claim 1 , further wherein the TFR layer comprises a continuous TFR region lying in a single horizontal plane and contacting both of the spaced-apart salicide TFR heads.

14. The method of claim 1 , further comprising:
after depositing the dielectric layer over the salicide TFR heads, forming a sacrificial layer over the dielectric layer;
wherein the etching step removes a portion of the sacrificial layer below the photoresist trench; and
after depositing the TFR material to thereby form the TFR layer that bridges the pair of spaced-apart salicide TFR heads, removing (a) portions of the TFR material laterally outside the single TFR trench along with (b) remaining portions of the sacrificial layer.

15. A method for manufacturing a thin film resistor (TFR) structure, the method comprising:
forming a pair of TFR heads spaced apart from each other, each TFR head comprising a self-aligned silicide (salicide) structure;
depositing a dielectric layer over the salicide TFR heads;
patterning a photoresist trench into a photoresist layer using photo lithography, the patterned photoresist trench extending laterally over at least a portion of each salicide TFR head;
etching through the photoresist trench and through at least a portion of the dielectric layer and stopping at the salicide TFR heads, such that a surface of each salicide TFR head is exposed; and
depositing a TFR material into the TFR trench and onto the exposed surfaces of the salicide TFR heads, to thereby form a TFR layer that bridges the pair of spaced-apart salicide TFR heads; and
performing a Chemical Mechanical Polishing (CMP) process to remove portions of the TFR material outside the TFR trench.

16. The method of claim 15 , further comprising, after the removal process to remove portions of the TFR material outside the TFR trench, forming at least one of a phosphosilicate glass (PSG) layer or an un-doped silicate glass (USG) cap oxide layer over the structure.

17. The method of claim 15 , comprising annealing the structure after depositing the TFR material to alter a temperature coefficient of resistance (TCR) of the TFR material.

18. The method of claim 17 , comprising annealing the structure to achieve a TCR of the TFR material to a non-zero TCR value of less than |100 ppm/° C.|.

19. The method of claim 17 , comprising annealing the structure to achieve a TCR of the TFR material to a non-zero TCR value of less than |50 ppm/° C.|.

20. The method of claim 17 , comprising annealing the structure to achieve a TCR of the TFR material to a non-zero TCR value of less than |10 ppm/° C.|.

Assignees

• Microchip Tech Inc

Inventors

• Leng Yaojian

Classifications

• H01L21/76807

  Electricity · mapped topic

• H01L21/76804

  Electricity · mapped topic

• H01L23/53228

  Electricity · mapped topic

• H01L23/5228

  Electricity · mapped topic

• H01L28/24

  Electricity · mapped topic