Operating method of resistive memory storage apparatus

Patent metadata

Field	Value
Publication number	US-10643698-B2
Application number	US-201816103942-A
Country	US
Kind code	B2
Filing date	Aug 15, 2018
Priority date	Oct 11, 2017
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

An operating method of a resistive memory storage apparatus includes: applying a forming voltage to a memory cell and obtaining a cell current of the memory cell; and determining whether to adjust the forming voltage and apply the adjusted forming voltage to the memory cell according to a magnitude relationship between the cell current and a reference current. The memory cell to which the forming voltage is applied operates in a heavy forming mode and serves as a one-time programmable memory device.

First claim

What is claimed is:

1. An operating method of a resistive memory storage apparatus, comprising:
applying a forming voltage to a memory cell and obtaining a first cell current of the memory cell; and
determining whether to adjust the forming voltage and apply the adjusted forming voltage to the memory cell according to a magnitude relationship between the first cell current and a first reference current, wherein the memory cell to which the forming voltage is applied operates in a heavy forming mode and serves as a one-time programmable memory device.

2. The operating method of the resistive memory storage apparatus according to claim 1 , further comprising:
determining whether the first cell current is smaller than the first reference current;
if the first cell current is smaller than the first reference current, adjusting the forming voltage and applying the adjusted forming voltage to the memory cell; and
if the first cell current is greater than or equal to the first reference current, ending the operating method.

3. The operating method of the resistive memory storage apparatus according to claim 1 , further comprising:
repeating adjusting the forming voltage and applying the adjusted forming voltage to the memory cell until the first cell current becomes greater than or equal to the first reference current.

4. The operating method of the resistive memory storage apparatus according to claim 1 , wherein the forming voltage comprises a gate voltage and a bit line voltage, and applying the forming voltage to the memory cell comprises:
applying the gate voltage and the bit line voltage respectively to a gate of the memory cell and a bit line coupled to the gate of the memory cell, wherein voltage values of the gate voltage and the bit line voltage are determined according to a material of a dielectric layer of the memory cell.

5. The operating method of the resistive memory storage apparatus according to claim 1 , further comprising:
performing a reset operation on the memory cell operating in the heavy forming mode, wherein the memory cell on which the reset operation has been performed operates in the heavy forming mode and serves as a multiple-time programmable memory device.

6. The operating method of the resistive memory storage apparatus according to claim 5 , further comprising:
obtaining a second cell current of the memory cell; and
determining whether to perform the reset operation on the memory cell operating in the heavy forming mode according to a magnitude relationship between the second cell current and a second reference current,
wherein determining whether to perform the reset operation on the memory cell operating in the heavy forming mode according to the magnitude relationship between the second cell current and the second reference current comprises: determining whether the second cell current is smaller than the second reference current; if the second cell current is smaller than the second reference current, not performing the reset operation on the memory cell operating in the heavy forming mode and ending the operating method; and, if the second cell current is greater than or equal to the second reference current, performing the reset operation on the memory cell operating in the heavy forming mode.

7. The operating method of the resistive memory storage apparatus according to claim 5 , wherein the reset operation comprises:
setting a source line voltage of the memory cell, applying a reset voltage and the source line voltage respectively to a gate of the memory cell and a source line coupled to the gate of the memory cell, and obtaining a first reset current of the memory cell;
adjusting the source line voltage of the memory cell, applying the reset voltage and the adjusted source line voltage respectively to the gate of the memory cell and the source line coupled to the gate of the memory cell, and obtaining a second reset current of the memory cell; and
determining whether to adjust the source line voltage of the memory cell again or record a current value of the second reset current according to a magnitude relationship between the first reset current and the second reset current,
wherein determining whether to adjust the source line voltage of the memory cell again or record the current value of the second reset current according to the magnitude relationship between the first reset current and the second reset current comprises: determining whether the second reset current is smaller than the first reset current; if the second reset current is smaller than the first reset current, recording the current value of the second reset current; and, if the second reset current is equal to the first reset current, adjusting the source line voltage of the memory cell again.

8. The operating method of the resistive memory storage apparatus according to claim 7 , further comprising:
if the second reset current is equal to the first reset current, adjusting the source line voltage of the memory cell again, and repeating applying the reset voltage and the adjusted source line voltage respectively to the gate of the memory cell and the source line coupled to the gate of the memory cell until the second reset current becomes smaller than the first reset current.

9. The operating method of the resistive memory storage apparatus according to claim 7 , further comprising:
after recording the current value of the second reset current, adjusting the source line voltage of the memory cell again, applying the reset voltage and the adjusted source line voltage respectively to the gate of the memory cell and the source line coupled to the gate of the memory cell, and obtaining a third reset current of the memory cell; and
determining whether to adjust the source line voltage of the memory cell again or end the reset operation according to a magnitude relationship between the second reset current and the third reset current,
wherein determining whether to adjust the source line voltage of the memory cell again or end the reset operation according to the magnitude relationship between the second reset current and the third reset current comprises: determining whether the third reset current is greater than or equal to the second reset current; if the third reset current is greater than or equal to the second reset current, ending the reset operation; and, if the third reset current is smaller than the second reset current, adjusting the source line voltage of the memory cell again.

10. The operating method of the resistive memory storage apparatus according to claim 9 , further comprising:
if the third reset current is smaller than the second reset current, adjusting the source line voltage of the memory cell again, and repeating applying the reset voltage and the adjusted source line voltage respectively to the gate of the memory cell and the source line coupled to the gate of the memory cell until the third reset current becomes greater than or equal to the second reset current.

Assignees

• Winbond Electronics Corp
• Windbond Electronics Corp

Inventors

• Lin Lih-Wei
• Cheng Ju-Chieh
• Tsai Tsung-Huan
• Tseng I-Hsien

Classifications

• G11C13/0038

  Power supply circuits · CPC title

• G11C17/165

  Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002) · CPC title

• G11C13/0007 Primary

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C2013/0083

  Write to perform initialising, forming process, electro forming or conditioning · CPC title

• G11C13/0097 Primary

  Erasing, e.g. resetting, circuits or methods · CPC title