Fixing dead-zone in clock data recovery circuits

Patent metadata

Field	Value
Publication number	US-10637637-B2
Application number	US-201916261318-A
Country	US
Kind code	B2
Filing date	Jan 29, 2019
Priority date	Sep 24, 2018
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A method for fixing a dead-zone in a clock and data recovery (CDR) circuit is disclosed herein. The CDR circuit includes a CDR block and a phase interpolator, the CDR block is configured to generate phase codes based on signals from a phase detector, and the phase interpolator is configured to adjust a phase of a clock signal based on the phase codes. The method includes waiting for the CDR circuit to lock, reading a first phase code from the CDR block, changing the first phase code by a first amount to obtain a second phase code, and inputting the second phase code to the phase interpolator.

First claim

What is claimed is:

1. A method for fixing a dead-zone in a clock and data recovery (CDR) circuit, wherein the CDR circuit includes a CDR block and a phase interpolator, the CDR block is configured to generate phase codes based on signals from a phase detector, and the phase interpolator is configured to adjust a phase of a clock signal based on the phase codes, the method comprising:
waiting for the CDR circuit to lock;
reading a first phase code from the CDR block;
changing the first phase code by a first amount to obtain a second phase code; and
inputting the second phase code to the phase interpolator.

2. The method of claim 1 , wherein the first amount corresponds to a phase shift between 20 degrees and 90 degrees.

3. The method of claim 1 , wherein the signals from the phase detector indicate whether the clock signal is early or late with respect to a data signal.

4. The method of claim 1 , further comprising:
freezing the CDR block before reading the first phase code from the CDR block; and
unfreezing the CDR block after inputting the second phase code to the phase interpolator.

5. The method of claim 1 , further comprising:
after inputting the second phase code to the phase interpolator, waiting for the CDR circuit to lock;
reading a third phase code from the CDR block;
determining a first difference between the first phase code and the third phase code; and
comparing a magnitude of the first difference with a threshold.

6. The method of claim 5 , further comprising:
if the magnitude of the first difference is greater than the threshold, changing the third phase code by a second amount to obtain a fourth phase code; and
inputting the fourth phase code to the phase interpolator.

7. The method of claim 6 , wherein the first amount and the second amount are the same.

8. The method of claim 6 , further comprising:
after inputting the fourth phase code to the phase interpolator, waiting for the CDR circuit to lock;
reading a fifth phase code from the CDR block;
determining a second difference between the third phase code and the fifth phase code; and
comparing a magnitude of the second difference with the threshold.

9. The method of claim 5 , further comprising:
if the magnitude of the first difference is equal to or less than the threshold, changing the third phase code by a second amount to obtain a fourth phase code, wherein the second amount is in an opposite direction from the first amount; and
inputting the fourth phase code to the phase interpolator.

10. The method of claim 9 , wherein a magnitude of the second amount is approximately equal to half a magnitude of the first amount.

11. The method of claim 9 , further comprising:
after inputting the fourth phase code to the phase interpolator, waiting for the CDR circuit to lock;
reading a fifth phase code from the CDR block;
determining a second difference between the third phase code and the fifth phase code; and
comparing a magnitude of the second difference with the threshold.

12. A circuit for fixing a dead-zone in a clock and data recovery (CDR) circuit, wherein the CDR circuit includes a CDR block and a phase interpolator, the CDR block is configured to generate phase codes based on signals from a phase detector, and the phase interpolator is configured to adjust a phase of a clock signal based on the phase codes, the circuit comprising:
a controller; and
a multiplexer configured to selectively couple the CDR block or the controller to the phase interpolator;
wherein the controller is configured to:
instruct the multiplexer to couple the CDR block to the phase interpolator and wait for the CDR circuit to lock;
read a first phase code from the CDR block;
change the first phase code by a first amount to obtain a second phase code;
instruct the multiplexer to couple the controller to the phase interpolator and input the second phase code to the phase interpolator; and
instruct the multiplexer to couple the CDR block to the phase interpolator after the second phase code is input to the phase interpolator.

13. The circuit of claim 12 , wherein the first amount corresponds to a phase shift between 20 degrees and 90 degrees.

14. The circuit of claim 12 , wherein the signals from the phase detector indicate whether the clock signal is early or late with respect to a data signal.

15. The circuit of claim 12 , wherein the controller is configured to:
freeze the CDR block before reading the first phase code from the CDR block; and
unfreeze the CDR block after inputting the second phase code to the phase interpolator.

16. The circuit of claim 12 , wherein the controller is configured to:
wait for the CDR circuit to lock after the second phase code is input to the phase interpolator;
read a third phase code from the CDR block;
determine a first difference between the first phase code and the third phase code; and
compare a magnitude of the first difference with a threshold.

17. The circuit of claim 16 , wherein the controller is configured to:
if the magnitude of the first difference is greater than the threshold, change the third phase code by a second amount to obtain a fourth phase code; and
instruct the multiplexer to couple the controller to the phase interpolator and input the fourth phase code to the phase interpolator.

18. The circuit of claim 17 , wherein the first amount and the second amount are the same.

19. The circuit of claim 17 , wherein the controller is configured to:
instruct the multiplexer to couple the CDR block to the phase interpolator after the fourth phase code is input to the phase interpolator and wait for the CDR circuit to lock;
read a fifth phase code from the CDR block;
determine a second difference between the third phase code and the fifth phase code; and
compare a magnitude of the second difference with the threshold.

20. The circuit of claim 16 , wherein the controller is configured to:
if the magnitude of the first difference is equal to or less than the threshold, change the third phase code by a second amount to obtain a fourth phase code, wherein the second amount is in an opposite direction from the first amount; and
instruct the multiplexer to couple the controller to the phase interpolator and input the fourth phase code to the phase interpolator.

21. The circuit of claim 20 , wherein a magnitude of the second amount is approximately equal to half a magnitude of the first amount.

22. The circuit of claim 20 , wherein the controller is configured to:
instruct the multiplexer to couple the CDR block to the phase interpolator after the fourth phase code is input to the phase interpolator and wait for the CDR circuit to lock;
read a fifth phase code from the CDR block;
determine a second difference between the third phase code and the fifth phase code; and
compare a magnitude of the second difference with the threshold.

23. A circuit for fixing a dead-zone in a clock and data recovery (CDR) circuit, wherein the CDR includes a CDR block and a phase interpolator, the circuit comprising:
a controller configured to:
read a first phase code from the CDR block;
change the first phase code by an amount to obtain a second phase code; and
output the second phase code at an output of the controller; and

a multiplexer having a first input coupled to an output of the CDR block, a second input coupled to the output of the controller, and an output coupled to an input of the phase interpo

Assignees

• Qualcomm Inc

Inventors

• Goudarzi Hadi
• Boyette Jon
• Hailu Eskinder
• Puscar Julian

Classifications

• H04L7/0025 Primary

  interpolation of clock signal · CPC title

• H04L7/0004

  Initialisation of the receiver (H04L7/0075 and H04L7/10 take precedence) · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title