Clock data recovery with non-uniform clock tracking

Patent metadata

Field	Value
Publication number	US-2018219704-A1
Application number	US-201715422050-A
Country	US
Kind code	A1
Filing date	Feb 1, 2017
Priority date	Feb 1, 2017
Publication date	Aug 2, 2018
Grant date	—

Abstract

Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

First claim

1 . A method for adjusting a phase step size of a clock data recovery (CDR) circuit, wherein the CDR circuit recovers a clock signal from a data signal received by a receiver and samples the data signal using the recovered clock signal to recover data from the data signal, wherein the CDR circuit includes a loop filter, and wherein the loop filter includes an integration path that integrates phase error values of the CDR circuit, a proportional path that applies a proportional gain to the phase error values of the CDR circuit, and a summer that combines an output of the integration path and an output of the proportional path, the method comprising:
sensing a signal level on the integration path; and adjusting the phase step size of the CDR circuit based on the sensed signal level.

2 . The method of claim 1 , wherein adjusting the phase step size of the CDR circuit comprises:
switching the CDR circuit between a first phase step size and a second phase step size based on the sensed signal level using a modulator.

3 . The method of claim 2 , wherein the modulator comprises a sigma-delta modulator.

4 . A method for adjusting a phase step size of a clock data recovery (CDR) circuit, wherein the CDR circuit recovers a clock signal from a data signal received by a receiver and samples the data signal using the recovered clock signal to recover data from the data signal, the method comprising:
sensing a frequency offset of the CDR circuit; comparing the sensed frequency offset with a threshold; generating an input signal based on the comparison; modulating the input signal with the modulator to generate a control signal; and adjusting the phase step size of the CDR circuit by switching the CDR circuit between a first phase step size and a second phase step size based on the control signal.

5 . The method of claim 4 , wherein the input signal has a first input value if the sensed frequency offset is greater than the threshold, and a second input value if the sensed frequency offset is less than the threshold.

6 . The method of claim 5 , wherein the modulator comprises a sigma-delta modulator.

7 . The method of claim 4 , wherein switching the CDR circuit between the first phase step size and the second phase step size comprises:
switching the CDR circuit between a first phase step path and a second phase step path, the first phase step path providing the first phase step size and the second phase step path providing the second phase step size.

8 . The method of claim 4 , wherein sensing the frequency offset of the CDR circuit comprises:
sensing a signal level on an integration path of the CDR circuit.

9 . The method of claim 8 , wherein comparing the sensed frequency offset with the threshold comprises:
comparing the sensed signal level with the threshold.

10 . The method of claim 9 , wherein the modulator comprises a sigma-delta modulator.

11 . The method of claim 9 , wherein the input signal has a first input value if the sensed signal level is greater than the threshold, and a second input value if the sensed signal level is less than the threshold.

12 . The method of claim 11 , wherein the modulator comprises a sigma-delta modulator.

13 . An apparatus, comprising:
a phase step adjuster configured to adjust a phase step size of a clock data recovery (CDR) circuit, wherein the CDR circuit recovers a clock signal from a data signal received by a receiver and samples the data signal using the recovered clock signal to recover data from the data signal, wherein the CDR circuit includes a loop filter, and wherein the loop filter includes an integration path that integrates phase error values of the CDR circuit, a proportional path that applies a proportional gain to the phase error values of the CDR circuit, and a summer that combines an output of the integration path and an output of the proportional path; and a phase step controller configured to sense a signal level on the integration path, and to control the phase step adjuster to adjust the phase step size of the CDR circuit based on the sensed signal level.

14 . The apparatus of claim 13 , wherein the phase step adjuster is configured to adjust the phase step size of the CDR circuit by switching the CDR circuit between a first phase step size and a second phase step size based on the sensed signal level.

15 . An apparatus comprising:
a phase step adjuster configured to adjust a phase step size of a clock data recovery (CDR) circuit, wherein the CDR circuit recovers a clock signal from a data signal received by a receiver and samples the data signal using the recovered clock signal to recover data from the data signal; a comparison circuit configured to sense a frequency offset of the CDR circuit, to compare the sensed frequency offset with a threshold, and to generate an input signal based on the comparison; and a modulator configured to modulate the input signal to generate a control signal, wherein the phase step adjuster adjusts the phase step size of the CDR circuit based on the control signal.

16 . The apparatus of claim 15 , wherein the modulator comprises a sigma-delta modulator.

17 . The apparatus of claim 15 , wherein the phase step adjuster adjusts the phase step size of the CDR circuit by switching the CDR circuit between a first phase step size and a second phase step size.

18 . The apparatus of claim 15 , wherein the phase step adjuster comprises:
a first phase step path providing a first phase step size; a second phase step path providing a second phase step size; and a multiplexer configured to select between the first phase step path and the second phase step path based on the control signal.

19 . The apparatus of claim 18 , wherein the phase step adjuster is coupled between a loop filter and an integrator of the CDR circuit.

20 . (canceled)

21 . (canceled)

22 . The apparatus of claim 15 , wherein the input signal has a first input value if the sensed frequency offset is greater than the threshold, and a second input value if the sensed frequency offset is less than the threshold.

23 . The apparatus of claim 15 , wherein the sensed frequency offset of the CDR circuit comprises a sensed signal level on an integration path of the CDR circuit.

24 . (canceled)

25 . The apparatus of claim 23 , wherein the modulator comprises a sigma-delta modulator.

26 . (canceled)

27 . (canceled)

28 . (canceled)

Assignees

• Qualcomm Inc

Inventors

• Song Yu
• Zhu Zhi
• Li Miao
• Sun Li
• Song Deqiang
• Chang Chia Heng

Classifications

• H04L43/16

  Threshold monitoring · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title

• H04L7/0337

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title

• H04L25/03273 Primary

  with carrier recovery circuitry · CPC title

• H04L2027/0069

  Loop filters · CPC title