Multiple stage gate drive for cascode current sensing

Patent metadata

Field	Value
Publication number	US-10637368-B2
Application number	US-201916242915-A
Country	US
Kind code	B2
Filing date	Jan 8, 2019
Priority date	Jun 12, 2017
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A power converter includes an energy transfer element coupled between an input of the power converter and an output of the power converter. A control switch is coupled to a normally-on switch. The normally-on switch is coupled to the energy transfer element. A controller is coupled to control switching of the control switch to control a transfer of energy from the input of the power converter to the output of the power converter. The controller includes a drive circuit coupled to generate a drive signal in response to a control signal to control switching of the control switch. The drive signal in a first stage of a multiple stage gate drive is coupled not to fully enhance the control switch. The drive signal provided by a second stage of the multiple stage gate drive is coupled to fully enhance the control switch.

First claim

What is claimed is:

1. A power converter, comprising;
an energy transfer element coupled between an input of the power converter and an output of the power converter;
a control switch coupled to a normally-on switch, the normally-on switch further coupled to the energy transfer element; and
a controller configured to control switching of the control switch, the control switch configured to control a transfer of energy from the input of the power converter to the output of the power converter, wherein the controller comprises:
a drive circuit configured to generate a drive signal in response to a control signal to control switching of the control switch, wherein the drive signal in a first stage of a multiple stage gate drive is configured not to fully enhance the control switch, and wherein the drive signal provided by a second stage of the multiple stage gate drive is configured to fully enhance the control switch.

2. The power converter of claim 1 , wherein the control switch comprises one or more sense fingers coupled to the control switch, wherein the one or more sense fingers has a general ratio of resistance to a resistance of the normally-on switch.

3. The power converter of claim 2 , wherein the controller further comprises:
a current sense circuit configured to generate a current limit signal and an overcurrent signal in response to a source signal and one or more sense finger signals from the control switch; and
a control circuit configured to generate the control signal in response to the current limit signal and the overcurrent signal.

4. The power converter of claim 3 , wherein the one or more sense finger signals is generated by a drain of the one or more sense fingers coupled to a current source.

5. The power converter of claim 4 , wherein a value of the current source is representative of regulating an output voltage or an ON time of the power converter.

6. The power converter of claim 4 , wherein a value of the current source is representative of a maximum current limit of the power converter.

7. The power converter of claim 1 , the drive circuit comprising:
a first transistor with a first resistance configured to receive the control signal, the first transistor further configured to generate the drive signal of the first stage of the multiple stage gate drive;
a delay circuit configured to receive the control signal, the delay circuit further configured to output a delayed control signal; and
a second transistor with a second resistance configured to receive the delayed control signal, the second transistor further configured to generate the drive signal in the second stage of the multiple stage gate drive, wherein the first resistance of the first transistor is greater than the second resistance of the second transistor.

8. The power converter of claim 1 , wherein the normally-on switch is a high electron mobility transistor.

9. The power converter of claim 1 , wherein the normally-on switch is comprised of gallium nitride material (GaN).

10. The power converter of claim 1 , wherein the normally-on switch is a JFET comprised of a silicon carbide (SiC) material.

11. A controller for use in a power converter, comprising:
a current sense circuit configured to generate a current limit signal and an overcurrent signal in response to a source signal, a first sense finger signal, and a second sense finger signal;
a control circuit configured to generate a control signal in response to the current limit signal and the overcurrent signal; and
a drive circuit configured to generate a drive signal for a cascode circuit with a multiple stage gate drive in response to the control signal, wherein the drive signal in a first stage of the multiple stage gate drive is a weak turn on drive signal configured to turn the cascode circuit on slowly to reduce electromagnetic interference (EMI), and wherein the drive signal in a second stage of the multiple stage gate drive is a strong turn on drive signal configured to fully turn on the cascode circuit quickly to enable accurate current sensing of the cascode circuit.

12. The controller of claim 11 , wherein the cascode circuit comprises a low voltage switch coupled to a normally-on switch.

13. The controller of claim 12 , wherein the drive signal provided by the first stage of the multiple stage gate drive is configured not to fully enhance the low voltage switch to reduce the electromagnetic interference (EMI) of the cascode circuit.

14. The controller of claim 13 , wherein the drive signal provided by the first stage of the multiple stage gate drive is configured to provide a weak turn on of the low voltage switch.

15. The controller of claim 13 , wherein the drive signal provided by the second stage of the multiple stage gate drive is configured to fully enhance the low voltage switch to enable the cascode circuit to increase accuracy of current sensing.

16. The controller of claim 14 , wherein the drive signal provided by the second stage of the multiple stage gate drive is configured to provide a strong turn on of the low voltage switch.

17. The controller of claim 15 , the low voltage switch of the cascode circuit further comprising a first sense finger coupled to the low voltage switch, wherein a gate of the first sense finger is coupled to a gate of the low voltage switch.

18. The controller of claim 17 , the low voltage switch further comprising a second sense finger coupled to the low voltage switch, wherein a gate of the second sense finger is coupled to the gate of the low voltage switch.

19. The controller of claim 12 , wherein the normally-on switch is comprised of gallium nitride (GaN) material.

20. The controller of claim 17 , wherein the first sense finger signal is generated by a first current source coupled to a drain of the first sense finger.

21. The controller of claim 18 , wherein the second sense finger signal is generated by a second current source coupled to a drain of the second sense finger.

22. The controller of claim 12 , wherein the normally-on switch is comprised of silicon carbide (SiC) material.

Assignees

• Power Integrations Inc
• Power Integration Inc

Inventors

• Duvnjak Rajko

Classifications

• H02M1/08 Primary

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H03K17/6871

  the output circuit comprising more than one controlled field-effect transistor · CPC title

• H02M7/1626 Primary

  with automatic control of the output voltage or current · CPC title

• H03K17/102

  in field-effect transistor switches · CPC title

• H02H1/0007

  concerning the detecting means (in general G01R or other subclasses of G01; reed switches H01H71/2445) · CPC title