On-chip copy with data folding in three-dimensional non-volatile memory array

Patent metadata

Field	Value
Publication number	US-10635585-B2
Application number	US-201816010234-A
Country	US
Kind code	B2
Filing date	Jun 15, 2018
Priority date	May 15, 2018
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

In an on-chip copy process, performed by a storage device, data is copied from a plurality of Single Level Cell (SLC) blocks of non-volatile three-dimensional memory (e.g., 3D flash memory) in a respective memory die to a Multilevel Cell (MLC) block of the same memory die. A copy of source data from a respective SLC block is interleaved with a copy of source data from one or more other SLC blocks in the memory die to produce interleaved source data. Each source data copy that is interleaved is rotated by an offset assigned to the respective SLC block from which the source data is copied, and each respective SLC block in the plurality of SLC blocks is assigned a distinct offset. Each distinct set of the interleaved source data is written to a distinct respective MLC page of the MLC block.

First claim

What is claimed is:

1. A method for managing data in a storage device having one or more memory die, each memory die comprising a non-volatile three-dimensional memory having a plurality of blocks, each block including a plurality of word lines, the method comprising:
performing an on-chip copy of data from a plurality of Single Level Cell (SLC) blocks of the non-volatile three-dimensional memory in a respective memory die to one Multilevel Cell (MLC) block of the non-volatile three-dimensional memory in the respective memory die by performing a set of operations comprising:
mapping source data from the plurality of SLC blocks to data groups, such that each data group includes pages of a predefined number of word lines of a respective SLC block of the plurality of SLC blocks;
interleaving a copy of source data from a data group of a respective SLC block of the plurality of SLC blocks with a copy of source data from a data group of one or more other SLC blocks of the plurality of SLC blocks to produce interleaved source data, the interleaved source data including a plurality of distinct sets of interleaved source data;
wherein each source data copy that is interleaved is rotated by an offset assigned to the respective SLC block from which the source data is copied, and each respective SLC block in the plurality of SLC blocks is assigned a distinct offset; and
writing each distinct set of the interleaved source data to a distinct respective MLC page of the MLC block, including writing a first set of the interleaved source data to a first individual MLC page of the MLC block and writing a second set of the interleaved source data to a second individual MLC page of the MLC block, the first set having only non-parity data from the plurality of SLC blocks, and the second set having parity data from one SLC block of the plurality of SLC blocks and non-parity data from one or more other SLC blocks of the plurality of SLC blocks.

2. The method of claim 1 , wherein the writing includes:
writing a third set of the interleaved source data to a third individual page, the third set having parity data from two of SLC blocks of the plurality of SLC blocks and non-parity data from one or more other SLC blocks of the plurality of SLC blocks.

3. The method of claim 1 , wherein
the respective memory die in the non-volatile three-dimensional memory includes three SLC blocks, the MLC block includes respective MLC pages, each respective MLC page of the MLC block including a lower page, middle page and upper page, each distinct set of interleaved source data includes first, second and third pages of source data, including one page from each of the three SLC blocks, which are written to the lower page, the middle page and the upper page, respectively, of a corresponding MLC page of the MLC block.

4. The method of claim 3 , wherein
each SLC block of the three SLC blocks includes two pages of parity data, and the plurality of distinct sets of interleaved source data include two sets of interleaved source data that each include a distinct page of the two pages of parity data from a first SLC block of the three SLC blocks.

5. The method of claim 4 , wherein the second set of the interleaved source data written to the second individual MLC page of the MLC block includes one of the two pages of parity data from the first SLC block of the three SLC blocks and one page of non-parity data from each of the other SLC blocks of the three SLC blocks.

6. The method of claim 4 , wherein the third set of interleaved data includes one of the two pages of parity data from the first SLC block of the three SLC blocks, stored at a first word line position in the first SLC block, and one of the two pages of parity data from a second SLC block of the three SLC blocks, stored at a second word line position in the second SLC block, wherein the second word line position is different from the first word line position.

7. The method of claim 1 , wherein
performing the on-chip copy includes copying data from 3P SLC blocks to P MLC blocks, where P is an integer greater than one, the 3P SLC blocks include P sets of 3 SLC blocks, and said mapping, interleaving and writing is applied to each set of 3 SLC blocks to write interleaved source data to one MLC block; and
the 3P SLC blocks include 6P pages of parity data, which are included in 4P distinct sets of interleaved source data by said interleaving, each of the 4P distinct sets of interleaved source data include one or two pages of parity data from one or two SLC blocks of the 3P SLC blocks.

8. The method of claim 7 , wherein the 3P SLC blocks and P MLC blocks are located in P or P/2 distinct memory die or P distinct memory planes, each having three SLC blocks of the 3P SLC blocks and one MLC block of the P MLC blocks.

9. The method of claim 1 , wherein
the respective memory die in the non-volatile three-dimensional memory includes four SLC blocks, the MLC block includes respective MLC pages, each respective MLC page of the MLC block including a lower page, lower-middle page, upper-middle page, and upper page, each distinct set of interleaved source data includes first, second, third and fourth pages of source data, including one page from each of the four SLC blocks, which are written to the lower page, the lower-middle page, the upper-middle page, and the upper page, respectively, of a corresponding MLC page of the MLC block.

10. The method of claim 1 , wherein
performing the on-chip copy includes copying data from 4P SLC blocks to 4 MLC blocks, where P is an integer greater than one, the 4P SLC blocks include P sets of 4 SLC blocks, and said mapping, interleaving and writing is applied to each set of 4 SLC blocks to write interleaved source data to one MLC block; and
the 4P SLC blocks include 8P pages of parity data, which are included in 5P distinct sets of interleaved source data by said interleaving, each of the 5P distinct sets of interleaved source data include one or two pages of parity data from one or two SLC blocks of the 4P SLC blocks.

11. The method of claim 10 , wherein the 4P SLC blocks and P MLC blocks are located in P or P/2 distinct memory die or P distinct memory planes, each having four SLC blocks of the 4P SLC blocks and one MLC block of the P MLC blocks.

12. A storage device comprising:
one or more memory die, each memory die comprising a non-volatile three-dimensional memory having a plurality of blocks, each block including a plurality of word lines;
one or more processors; and
controller memory storing one or more programs, which when executed by the one or more processors cause the storage device to perform operations comprising:
performing an on-chip copy of data from a plurality of Single Level Cell (SLC) blocks of the non-volatile three-dimensional memory in a respective memory die to one Multilevel Cell (MLC) block of the non-volatile three-dimensional memory in the respective memory die by performing a set of operations comprising:
mapping source data from the plurality of SLC blocks to data groups, such that each data group includes pages of a predefined number of word lines of a respective SLC block of the plurality of SLC blocks;
interleaving a copy of source data from a data group of a respective SLC block of the plurality of SLC blocks with a copy of source data from a data group of one or more other SLC blocks of the plurality of SLC blocks to produce interleaved source data, the interleaved source data including a plurality of distinct sets of interleaved source data;
wherein each source data copy that is interleaved is rotated by an offset assigned to the respective SLC block from which the source data is copied, and each respect

Assignees

• Western Digital Tech Inc

Inventors

• Kashyap Abhilash R
• Dusija Gautam A
• Raghu Deepak
• Yip Chris Nga Yee

Classifications

• G06F2212/2022

  Flash memory · CPC title

• G06F12/0607 Primary

  Interleaved addressing · CPC title

• G06F2212/7205

  Cleaning, compaction, garbage collection, erase control · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F3/065

  Replication mechanisms · CPC title