Memory system performing error correction of address mapping table

Patent metadata

Field	Value
Publication number	US-10635530-B2
Application number	US-201715718143-A
Country	US
Kind code	B2
Filing date	Sep 28, 2017
Priority date	Nov 7, 2016
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A memory system includes a nonvolatile memory device, a dynamic random access memory (DRAM) configured to store an address mapping table for an access to the nonvolatile memory device, and a controller configured to store, in the DRAM, the address mapping table that is divided in units of address mapping data, each of the units having a size of an interface of the DRAM, read, from the stored address mapping table, target address mapping data corresponding to a logical address that is received from a host, the target address mapping data including a target parity and physical addresses of the nonvolatile memory device, and perform an error correction on the read target address mapping data, using the target parity.

First claim

What is claimed is:

1. A memory system comprising:
a nonvolatile memory device;
a dynamic random access memory (DRAM) configured to store an address mapping table for an access to the nonvolatile memory device; and
a central processing unit implementing a controller configured to:
store, in the DRAM, the address mapping table that is divided in units of address mapping data, each of the units having a size of an interface of the DRAM;
read, from the stored address mapping table, target address mapping data corresponding to a logical address that is received from a host, the target address mapping data comprising a target parity and physical addresses of the nonvolatile memory device;
divide the target address mapping data into the target parity and a target physical address chunk comprising a target physical address corresponding to the logical address;
detecting and correcting an error of the target physical address chunk, using the target parity; and
replace, with a new physical address, the target physical address corresponding to the logical address, in the target physical address chunk of which the error is corrected, to generate a new physical address chunk.

2. The memory system of claim 1 , wherein the target parity is generated based on the target physical address chunk.

3. The memory system of claim 1 , wherein the controller is further configured to:
generate a new parity, based on the new physical address chunk;
combine the new physical address chunk and the new parity to generate new address mapping data; and
store the new address mapping data in the DRAM.

4. The memory system of claim 3 , wherein the controller is further configured to replace the target address mapping data in the DRAM with the new address mapping data.

5. The memory system of claim 1 , wherein a capacity of the address mapping table is proportional to a capacity of the nonvolatile memory device.

6. A memory system comprising:
a nonvolatile memory device;
a DRAM configured to store an address mapping table for an access to the nonvolatile memory device; and
a central processing unit implementing a controller configured to:
store, in the DRAM, the address mapping table that is divided in units of address mapping data, each of the units having a size of an interface of the DRAM;
access the nonvolatile memory device by performing an error detection and correction on target address mapping data corresponding to the access among the stored address mapping table, the target address mapping data comprising physical addresses of the nonvolatile memory device and a target parity corresponding to the physical addresses,

wherein the controller comprises a mapping table error correction circuit connected to the DRAM and configured to perform the error detection and correction on the target address mapping data,
wherein the mapping table error correction circuit comprises a mapping table error correction decoder configured to:
divide the target address mapping data into a target physical address chunk and the target parity: and
detect and correct an error of the target physical address chunk, using the target parity, and

wherein the mapping table error correction circuit further comprises an address processor configured to replace, with a new physical address, a target physical address corresponding to the access, in the target physical address chunk of which the error is corrected, to generate a new physical address chunk.

7. The memory system of claim 6 , wherein the address processor is further configured to obtain the target physical address corresponding to the access, from the target physical address chunk of which the error is corrected.

8. The memory system of claim 6 , wherein the mapping table error correction circuit further comprises a mapping table error correction encoder configured to:
generate a new parity, based on the new physical address chunk; and
combine the new physical address chunk and the new parity to generate new address mapping data.

9. The memory system of claim 8 , wherein the mapping table error correction encoder is further configured to replace the target address mapping data in the DRAM with the new address mapping data to store the new address mapping data in the DRAM.

10. The memory system of claim 6 , wherein the mapping table error correction circuit is further configured to perform the error detection and correction on the target address mapping data through one read operation from the DRAM.

11. The memory system of claim 6 , wherein the memory system comprises a solid state drive or a universal flash storage.

12. A method of controlling a memory system comprising a nonvolatile memory device and a dynamic random access memory (DRAM), the method comprising:
receiving, from a host, a request to translate a logical address that is used by the host to a target physical address of the nonvolatile memory device, the request comprising a new physical address corresponding to the logical address, for a write operation;
reading target address mapping data corresponding to the logical address of the received request, from pieces of address mapping data that are stored in the DRAM, the target address mapping data comprising a target parity and target physical addresses of the nonvolatile memory device;
correcting an error of the target physical addresses included in the target address mapping data, using the target parity;
outputting the target physical address corresponding to the logical address among the target physical addresses of which the error is corrected; and
replacing, with the new physical address of the received request, the target physical address corresponding to the logical address among the target physical addresses of which the error is corrected, to generate new physical addresses of the nonvolatile memory device.

13. The method of claim 12 , wherein each of the pieces of the address mapping data has a size of a burst length of the DRAM.

14. The method of claim 12 , further comprising:
generating a new parity, based on the new physical addresses;
combining the new physical addresses and the new parity to generate new address mapping data; and
replacing the target address mapping data in the DRAM with the new address mapping data to store the new address mapping data in the DRAM.

15. The method of claim 12 , wherein the correcting is performed through one read operation from the DRAM.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyunsik
• Kim Tae-Hwan

Classifications

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/1016 Primary

  Error in accessing a memory location, i.e. addressing error · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title