Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and prediction

Patent metadata

Field	Value
Publication number	US-10635446-B2
Application number	US-201514863755-A
Country	US
Kind code	B2
Filing date	Sep 24, 2015
Priority date	Sep 24, 2015
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and prediction is disclosed. In one aspect, a pipeline reconfiguration circuit is communicatively coupled to an execution pipeline providing multiple selectable pipeline configurations. The pipeline reconfiguration circuit generates a phase identifier (ID) for a phase based on a preceding phase. The phase ID is used as an index into an entry of a pipeline configuration prediction (PCP) table to determine whether training for the phase is ongoing. If so, the pipeline reconfiguration circuit performs multiple training cycles, each employing a pipeline configuration from the selectable pipeline configurations for the execution pipeline, to determine a preferred pipeline configuration for the phase. If training for the phase is complete, the pipeline reconfiguration circuit reconfigures the execution pipeline into the preferred pipeline configuration indicated by the entry before the phase is executed.

First claim

What is claimed is:

1. A pipeline reconfiguration circuit of an out-of-order (OOO) computer processor,
the pipeline reconfiguration circuit comprising a pipeline configuration prediction (PCP) table comprising a plurality of entries, and communicatively coupled to an execution pipeline that provides a plurality of selectable pipeline configurations; and
the pipeline reconfiguration circuit configured to, for each phase of a plurality of phases of committed instructions within the execution pipeline:
generate a phase identifier (ID) for a preceding phase immediately prior to the phase by hashing a plurality of program counters of a plurality of committed backward branch instructions within the preceding phase;
determine whether a training state indicator of an entry corresponding to the phase ID among the plurality of entries of the PCP table indicates that training for the phase is ongoing, wherein the phase ID is used as an index into the PCP table to access the entry corresponding to the phase ID among the plurality of entries of the PCP table;
responsive to determining that the training state indicator for the entry indicates that training for the phase is ongoing, perform a plurality of training cycles each using a pipeline configuration selected from among the plurality of selectable pipeline configurations of the execution pipeline to determine a preferred pipeline configuration; and
responsive to determining that the training state indicator for the entry indicates that training for the phase is not ongoing, reconfigure the execution pipeline into the preferred pipeline configuration indicated by the entry.

2. The pipeline reconfiguration circuit of claim 1 , configured to perform the plurality of training cycles each using the pipeline configuration selected from among the plurality of selectable pipeline configurations of the execution pipeline to determine the preferred pipeline configuration by:
selecting the pipeline configuration from among the plurality of selectable pipeline configurations of the execution pipeline based on the training state indicator for the entry;
reconfiguring the execution pipeline into the selected pipeline configuration;
measuring a performance metric of the selected pipeline configuration after execution of the phase;
updating the entry corresponding to the phase ID based on the measured performance metric; and
updating the training state indicator for the entry to indicate a next training state.

3. The pipeline reconfiguration circuit of claim 2 , wherein the measured performance metric comprises an execution cycle count.

4. The pipeline reconfiguration circuit of claim 1 , wherein the plurality of committed backward branch instructions within the preceding phase are selected from the group consisting of one or more most recent backward not-taken conditional branch instructions, one or more most recent backward call instructions, and one or more most recent backward return instructions, and combinations thereof.

5. The pipeline reconfiguration circuit of claim 1 , further comprising a phase ID shift register configured to store a plurality of generated phase IDs;
the execution pipeline configured to generate the phase ID by hashing one or more generated phase IDs stored in the phase ID shift register.

6. The pipeline reconfiguration circuit of claim 1 , wherein the plurality of selectable pipeline configurations are selected from the group consisting of a plurality of execution pipeline issue width configurations, a plurality of reservation station bank configurations, a plurality of instruction ordering configurations, a plurality of hardware prefetcher setting configurations, a plurality of branch predictor setting configurations, and a plurality of memory dependence predictor aggressiveness setting configurations, and combinations thereof.

7. The pipeline reconfiguration circuit of claim 1 , further configured to, prior to determining whether the training state indicator of the entry corresponding to the phase ID among the plurality of entries of the PCP table indicates that training for the phase is ongoing:
determine whether the entry corresponding to the phase ID in the PCP table is in use; and
responsive to determining that the entry corresponding to the phase ID is not in use, initialize the training state indicator for the entry.

8. The pipeline reconfiguration circuit of claim 1 , further configured to periodically invalidate the plurality of entries of the PCP table to force retraining.

9. The pipeline reconfiguration circuit of claim 1 , further configured to:
responsive to determining that the training state indicator for the entry indicates that training for the phase is not ongoing, increment a reuse count indicator for the entry;
determine whether the reuse count indicator for the entry has reached a threshold value; and
responsive to determining that the reuse count indicator for the entry has reached the threshold value, invalidate the entry.

10. The pipeline reconfiguration circuit of claim 1 , further comprising an update required indicator;
the pipeline reconfiguration circuit further configured to:
responsive to determining that the training state indicator for the entry indicates that training for the phase is ongoing, set the update required indicator;
responsive to determining that the training state indicator for the entry indicates that training for the phase is not ongoing, clear the update required indicator; and
update the training state indicator for the entry responsive to the update required indicator being in a set state.

11. The pipeline reconfiguration circuit of claim 1 integrated into an integrated circuit (IC).

12. The pipeline reconfiguration circuit of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a smart phone; a tablet; a phablet; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; and an automobile.

13. An out-of-order (OOO) processor-based system, comprising:
an execution pipeline that provides a plurality of selectable pipeline configurations;
a pipeline reconfiguration circuit comprising a pipeline configuration prediction (PCP) table comprising a plurality of entries, and communicatively coupled to the execution pipeline; and
the pipeline reconfiguration circuit configured to, for each phase of a plurality of phases of committed instructions within the execution pipeline:
generate a phase identifier (ID) for a preceding phase immediately prior to the phase by hashing a plurality of program counters of a plurality of committed backward branch instructions within the preceding phase;
determine whether a training state indicator of an entry corresponding to the phase ID among the plurality of entries of the PCP table indicates that training for the phase is ongoing, wherein the phase ID is used as an index into the PCP table to access the entry corresponding to the phase ID among the plurality of entries of the PCP table;
responsive to determining that the training state indicator for the entry indicates that training for the phase is ongoing, perform a plurality of training cycles each using a pipeline configuration selected from among the plurality of selecta

Assignees

• Qualcomm Inc

Inventors

• Priyadarshi Shivam
• Krishna Anil
• Damodaran Raguram

Classifications

• G06F11/3024

  where the computing system component is a central processing unit [CPU] · CPC title

• G06F9/3814

  Implementation provisions of instruction buffers, e.g. prefetch buffer; banks · CPC title

• G06F9/3867 Primary

  using instruction pipelines · CPC title

• G06F9/3885

  using a plurality of independent parallel functional units · CPC title

• G06F11/3452

  Performance evaluation by statistical analysis · CPC title