Combined analog architecture and functionality in a mixed-signal array

Patent metadata

Field	Value
Publication number	US-10634722-B1
Application number	US-201916420910-A
Country	US
Kind code	B1
Filing date	May 23, 2019
Priority date	May 5, 2009
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.

First claim

What is claimed is:

1. A circuit comprising:
a plurality of programmable digital blocks configured according to at least one first configuration register, wherein at least one programmable digital block is for issuing a direct memory access (DMA) request in response to an event detected by the plurality of programmable digital blocks;
a DMA controller coupled to the at least one programmable digital block, the DMA controller for retrieving configuration information from a memory and writing the configuration information to at least one second configuration register upon receipt of the DMA request.

2. The circuit of claim 1 , wherein the at least one second configuration register is distinct from the at least one first configuration register.

3. The circuit of claim 1 , wherein the at least one first configuration register includes the at least one second configuration register.

4. The circuit of claim 1 , further comprising:
a digital system interconnect (DSI) coupled to the plurality of programmable digital blocks and the DMA controller.

5. The circuit of claim 1 , further comprising:
a peripheral HUB (PHUB) coupled to the plurality of programmable digital blocks and the DMA controller.

6. The circuit of claim 1 , wherein the plurality of programmable digital blocks are programmable logic arrays.

7. The circuit of claim 1 , wherein the at least one programmable digital block is coupled to an interrupt controller for generating an interrupt signal.

8. The circuit of claim 1 , wherein the configuration information written to the at least one second configuration register is for dynamically reconfiguring the at least one of the plurality of programmable digital blocks in response to the DMA request.

9. The circuit of claim 8 , wherein the dynamically reconfiguring the plurality of programmable digital blocks in response to the DMA request is performed without central processing unit (CPU) control.

10. The circuit of claim 8 , wherein the at least one of the plurality of programmable digital blocks is distinct from at least one other of the plurality of programmable digital blocks for issuing a DMA request.

11. A method comprising:
receiving a direct memory access (DMA) request from at least one of a plurality of programmable digital blocks in response to an event detected by the plurality of programmable digital blocks;
retrieving configuration information using a DMA controller from a memory in response to the DMA request; and
writing the configuration information using the DMA controller from the memory to at least one configuration register, the at least one configuration register corresponding to at least one circuit element other than the plurality of programmable digital blocks.

12. The method of claim 11 , further comprising:
reconfiguring the at least one circuit element other than the plurality of programmable digital blocks in response to the configuration information written to the at least one configuration register, wherein the reconfiguration is performed without action by a central processing unit (CPU).

13. The method of claim 11 , wherein the DMA request is received through a digital system interconnect (DSI) coupled to the at least one of the plurality of programmable digital blocks.

14. The method of claim 11 , further comprising:
generating an interrupt with an interrupt controller coupled to the at least one of the plurality of programmable digital blocks, the interrupt provided to a central processing unit (CPU).

15. A system comprising:
a central processing unit (CPU);
a memory;
a programmable circuit comprising a plurality of programmable digital blocks configured according to at least one first configuration register, wherein at least one programmable digital block is for issuing a direct memory access (DMA) request in response to an event detected by the plurality of programmable digital blocks;
a DMA controller coupled to the at least one programmable digital block, the DMA controller for retrieving configuration information from a memory and writing the configuration information to at least one second configuration register upon receipt of the DMA request.

16. The system of claim 15 , wherein the at least one second configuration register is distinct from the at least one first configuration register.

17. The system of claim 15 , wherein the at least one first configuration register includes the at least one second configuration register.

18. The system of claim 15 , further comprising:
a digital system interconnect (DSI) coupled to the plurality of programmable digital blocks and the DMA controller.

19. The system of claim 15 , further comprising:
a peripheral HUB (PHUB) coupled to the CPU, the plurality of programmable digital blocks, and the DMA controller.

20. The system of claim 15 , wherein the plurality of programmable digital blocks are programmable logic arrays.

21. The system of claim 15 , wherein at least one programmable digital block of the plurality of programmable digital blocks is coupled to an interrupt controller for generating an interrupt signal.

22. The system of claim 21 , wherein the interrupt signal is provided to the CPU.

23. The system of claim 15 , wherein the configuration information written to the at least one second configuration register is for dynamically reconfiguring the at least one of the plurality of programmable digital blocks in response to the DMA request.

24. The system of claim 23 , wherein the dynamically reconfiguring the programmable circuit in response to the DMA request is performed without central processing unit (CPU) action.

25. The system of claim 15 , wherein the DMA controller is coupled to an interrupt controller for providing interrupt signals to the CPU.

Assignees

• Cypress Semiconductor Corp

Inventors

• Kutz Harold
• Williams Timothy John
• Sullam Bert
• Snyder Warren S
• Shutt James H
• Byrkett Bruce E
• Mar Monte
• Thiagarajan Eashwar
• Kohagen Nathan Wayne
• Wright David G
• Hastings Mark E
• Seguine Dennis R

Classifications

• H03K19/173

  using elementary logic circuits as components · CPC title

• G01R31/31721

  Power aspects, e.g. power supplies for test circuits, power saving during test (for scan test G01R31/318575) · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title