Memory device having electrically floating body transistor

Patent metadata

Field	Value
Publication number	US-10629599-B2
Application number	US-201816224534-A
Country	US
Kind code	B2
Filing date	Dec 18, 2018
Priority date	Apr 8, 2012
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

First claim

That which is claimed is:

1. A semiconductor memory cell comprising:
a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; and
a back bias region;
wherein said floating body region acts as a base region of a first bipolar transistor that maintains the state of said memory cell;
wherein said back-bias region acts as a collector region of said first bipolar transistor and has a lower band gap than said floating body region;
wherein said floating body region acts as a base region of a second bipolar transistor that is used to perform at least one of reading and writing the state of said memory cell; and
wherein current flow through said second bipolar transistor is larger when said memory cell is in one of said first and second states than when said memory cell is in the other of said first and second states.

2. The semiconductor memory cell of claim 1 , further comprising a gate region positioned above said floating body region.

3. The semiconductor memory cell of claim 1 , wherein said back-bias region is configured to maintain a charge in said floating body region.

4. The semiconductor memory cell of claim 1 , wherein said first and second states are stable states.

5. The semiconductor memory cell of claim 1 , wherein a product of forward emitter gain and impact ionization efficiency of said first bipolar transistor approaches unity when said memory cell is in one of said first and second states, and wherein impact ionization, when said memory cell is in the other of said first and second states is less than the impact ionization when said memory cell is in said one of said first and second states.

6. The semiconductor memory cell of claim 1 , wherein said memory cell states are maintained through impact ionization.

7. The semiconductor memory cell of claim 1 , wherein said semiconductor memory cell is formed in a fin structure.

8. A semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes: a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; and a back bias region; wherein said floating body region acts as a base region of a first bipolar transistor that maintains the state of said memory cell; wherein said back-bias region acts as a collector region of said first bipolar transistor and has a lower band gap than said floating body region; wherein said floating body region acts as a base region of a second bipolar transistor that is used to perform at least one of reading and writing the state of said memory cell; and wherein current flow through said second bipolar transistor is larger when said memory cell is in one of said first and second states than when said memory cell is in the other of said first and second states; wherein said back bias region is commonly connected to at least two of said memory cells.

9. The semiconductor memory array of claim 8 , wherein each of said semiconductor memory cells further comprises a gate region positioned above said floating body region.

10. The semiconductor memory array of claim 8 , wherein said back-bias region is configured to maintain a charge in said floating body region.

11. The semiconductor memory array of claim 8 , wherein said first and second states are stable states.

12. The semiconductor memory array of claim 8 , wherein a product of forward emitter gain and impact ionization efficiency of said first bipolar transistor approaches unity when said memory cell is in one of said first and second states, and wherein impact ionization, when said memory cell is in the other of said first and second states is less than the impact ionization when said memory cell is in said one of said first and second states.

13. The semiconductor memory array of claim 8 , wherein said memory cell states are maintained through impact ionization.

14. The semiconductor memory array of claim 8 , wherein said semiconductor memory cells are formed in at least one fin structure.

15. An integrated circuit comprising:
a semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; and
a back bias region;
wherein said floating body region acts as a base region of a first bipolar transistor that maintains the state of said memory cell;
wherein said back-bias region acts as a collector region of said first bipolar transistor and has a lower band gap than said floating body region;
wherein said floating body region acts as a base region of a second bipolar transistor that is used to perform at least one of reading and writing the state of said memory cell;
wherein current flow through said second bipolar transistor is larger when said memory cell is in one of said first and second states than when said memory cell is in the other of said first and second states;
wherein said back bias region is commonly connected to at least two of said memory cells; and

a control circuit configured to provide electrical signals to said back bias region.

16. The integrated circuit of claim 15 , wherein each of said semiconductor memory cells further comprises a gate region positioned above said floating body region.

17. The integrated circuit of claim 15 , wherein said back-bias region is configured to maintain a charge in said floating body region.

18. The integrated circuit of claim 15 , wherein said first and second states are stable states.

19. The integrated circuit of claim 15 , wherein said memory cell states are maintained through impact ionization.

20. The integrated circuit of claim 15 , wherein at least one of said semiconductor memory cells is formed in a fin structure.

Assignees

• Zeno Semiconductor Inc

Inventors

• Widjaja Yuniarto
• Han Jin-Woo
• Louie Benjamin S

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0433

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/404 Primary

  with one charge-transfer gate, e.g. MOS transistor, per cell · CPC title