Verifying memory access

Patent metadata

Field	Value
Publication number	US-10628084-B2
Application number	US-201816156046-A
Country	US
Kind code	B2
Filing date	Oct 10, 2018
Priority date	Oct 18, 2017
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

A memory arrangement having a memory cell field with columns and rows of writable memory cells, a memory controller which is configured to initiate an access to a first group of memory cells of a row of memory cells and, together with the access to the first group of memory cells, to initiate a read access to a second group of memory cells of the row of memory cells, and a verification circuit which is configured to check whether the access to the first group of memory cells has been performed on the correct row of memory cells on the basis of whether values read during the read access to the second group of memory cells match values previously stored by the second group of memory cells.

First claim

The invention claimed is:

1. A memory arrangement, comprising:
a memory cell field with columns and rows of writable memory cells;
a memory controller which is configured:
to initiate an access to a first group of memory cells of a row of memory cells; and
together with the access to the first group of memory cells, to initiate a read access to a second group of memory cells of the row of memory cells; and

a verification circuit which is configured to check whether the access to the first group of memory cells has been performed on the correct row of memory cells on the basis of whether values read during the read access to the second group of memory cells match values previously stored by the second group of memory cells.

2. The memory arrangement as claimed in claim 1 , wherein the access to the first group of memory cells is a write access.

3. The memory arrangement as claimed in claim 1 , wherein the first group of memory cells and the second group of memory cells form part of a memory word of the memory cell field.

4. The memory arrangement as claimed in claim 2 , wherein the write access to the first group of memory cells is a partial write access to the memory word.

5. The memory arrangement as claimed in claim 2 , wherein the write access to the first group of memory cells is an invalidation of the memory word.

6. The memory arrangement as claimed in claim 5 , wherein the memory word comprises redundancy information and the invalidation entails a modification of the memory word so that the redundancy information for the memory word is invalid.

7. The memory arrangement as claimed in claim 2 , wherein the write access to the first group of memory cells is an invalidation of redundancy information of the memory word which is stored in the first group of memory cells.

8. The memory arrangement as claimed in claim 2 , wherein the write access to the first group of memory cells is an invalidation of an error correction code or an error detection code of the memory word which is stored in the first group of memory cells.

9. The memory arrangement as claimed in claim 1 , wherein the memory cell field has bit lines and word lines, wherein a bit line is assigned to each column of memory cells and a word line is assigned to each row of memory cells, and wherein the memory controller is configured to initiate the access to the first group of memory cells and the read access to the second group of memory cells together by activating a word line which is assigned to the row of memory cells to which the first group of memory cells and the second group of memory cells belong.

10. The memory arrangement as claimed in claim 9 , wherein the memory controller is configured to initiate the access to the first group of memory cells and the read access to the second group of memory cells for the same activation of a word line.

11. The memory arrangement as claimed in claim 1 , wherein the memory cells of the first group of memory cells and the memory cells of the second group of memory cells alternate at least partially along the row of memory cells.

12. The memory arrangement as claimed in claim 1 , wherein the verification circuit comprises a memory which is configured to store the values stored by the second group of memory cells.

13. The memory arrangement as claimed in claim 1 , wherein the memory controller is configured to pre-initialize the second group of memory cells with a pattern identifying the second group of memory cells.

14. A method for verifying a memory access, comprising:
initiating, by a memory controller, an access to a first group of memory cells of a row of memory cells of a memory cell field;
together with the access to the first group of memory cells, initiating, by the memory controller, a read access to a second group of memory cells of the row of memory cells; and
checking, by the memory controller, whether the access to the first group of memory cells has been performed on the correct row of memory cells on the basis of whether values read during the read access to the second group of memory cells match values previously stored by the second group of memory cells.

15. The method as claimed in claim 14 , wherein the access to the first group of memory cells is a write access.

16. The method as claimed in claim 15 , wherein the write access to the first group of memory cells is an invalidation of redundancy information of the memory word which is stored in the first group of memory cells.

17. The method as claimed in claim 15 , wherein the write access to the first group of memory cells is an invalidation of an error correction code or an error detection code of the memory word which is stored in the first group of memory cells.

18. The method as claimed in claim 14 ,
wherein the memory cell field has bit lines and word lines, wherein a bit line is assigned to each column of memory cells and a word line is assigned to each row of memory cells, and
wherein the method further comprises the memory controller initiating the access to the first group of memory cells and the read access to the second group of memory cells together by activating a word line which is assigned to the row of memory cells to which the first group of memory cells and the second group of memory cells belong.

19. The method as claimed in claim 18 , further comprising the memory controller initiating the access to the first group of memory cells and the read access to the second group of memory cells for the same activation of a word line.

20. The method as claimed in claim 14 , further comprising the memory controller pre-initializing the second group of memory cells with a pattern identifying the second group of memory cells.

Assignees

• Infineon Technologies Ag

Inventors

• Hatsch Joel
• Meyer Bernd
• Otterstedt Jan
• Sonnekalb Steffen

Classifications

• G11C7/24 Primary

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F11/1004

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title