Cryogenic patterning of magnetic tunnel junctions

Patent metadata

Field	Value
Publication number	US-10622553-B2
Application number	US-201816230420-A
Country	US
Kind code	B2
Filing date	Dec 21, 2018
Priority date	Sep 7, 2016
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

Methods for forming magnetic tunnel junctions and structures thereof include cryogenic etching the layers defining the magnetic tunnel junction without lateral diffusion of reactive species.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a bottom electrode;
a magnetic tunnel junction disposed in an interlayer dielectric and on at least a portion of the bottom electrode, the magnetic tunnel junction comprising a first magnetic layer, an insulating layer on the first magnetic layer, and a second magnetic layer on the insulating layer;
a conductive mask including a bottom surface, a top surface and sidewalls extending from the bottom surface to the top surface, wherein the bottom surface is on the second magnetic layer of the magnetic tunnel junction; and
an upper electrode contacting an entirety of the sidewalls and the top surface of the conductive mask.

2. The semiconductor device of claim 1 , wherein the first and second magnetic layers are formed of a material comprising NiFe, IrMn, PtMn, Ru, Ta, TaN, CrMo, CoFe, CoFeB, CoZrTi, CoZrTa, CoZr, CoZrNb, CoZrMo, CoTi, CoNb, CoHf, CoW, FeCoN, FeCoAlN, CoP, FeCoP, CoPW, CoBW, CoPBW, FeTaN, FeCoBSi, FeNi, CoFeHfO, CoFeSiO, CoZrO, CoFeAlO, or combinations including at least one of the foregoing.

3. The semiconductor device of claim 1 , wherein the insulating layer comprises aluminum oxide, magnesium oxide, boron nitride, silicon oxynitride, silicon oxide, and combinations thereof.

4. The semiconductor device of claim 1 , wherein the conductive mask comprises copper, titanium, titanium nitride, tantalum, tantalum nitride, aluminum, tungsten, or combinations including at least one of the foregoing.

5. The semiconductor device of claim 1 , wherein the bottom electrode and the conductive mask comprise tantalum nitride.

6. The semiconductor device of claim 1 , wherein the conductive mask has a width equal to a width of the magnetic tunnel junction.

7. The semiconductor device of claim 1 , wherein the bottom electrode has a width greater than the first magnetic layer, the insulating layer, and the second magnetic layer.

8. The semiconductor device of claim 1 , wherein the conductive mask comprises a transition metal.

9. The semiconductor device of claim 1 , wherein the conductive mask has a thickness ranging from 20 nanometers to 100 nanometers.

10. The semiconductor device of claim 1 , wherein the conductive mask comprises a semiconductor material.

Assignees

• IBM

Inventors

• Annunziata Anthony J
• Kothandaraman Chandrasekharan
• Marchack Nathan P
• Miyazoe Hiroyuki

Classifications

• H01F41/308

  lift-off processes, e.g. ion milling, for trimming or patterning · CPC title

• H01F10/3254 Primary

  the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ] · CPC title

• H01F10/132

  containing cobalt · CPC title

• H01L43/12 Primary

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic