Semiconductor device with a multi-layered encapsulant and associated systems, devices, and methods

Patent metadata

Field	Value
Publication number	US-10622223-B2
Application number	US-201816009119-A
Country	US
Kind code	B2
Filing date	Jun 14, 2018
Priority date	Nov 17, 2017
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

First claim

We claim:

1. A semiconductor device, comprising:
a substrate including traces, wherein the traces protrude above a top surface of the substrate;
a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces and the top surface of the substrate;
a die attached over the substrate, wherein the die includes a bottom surface and pillars protruding from the die, wherein the pillars are electrically coupled to the traces via solder; and
a wafer-level underfill between the prefill material and the die, wherein:
the wafer-level underfill includes material that, at least under an initial state, reflows with the solder;
at least one of the wafer-level underfill and the prefill material is cured with the wafer-level underfill and the prefill material persisting as separate layers after curing, and
the wafer-level underfill directly contacts the bottom surface of the die and the pillars.

2. The semiconductor device of claim 1 wherein the prefill material corresponds to a first viscosity level for a manufacturing condition, wherein the first viscosity level is lower than a second viscosity level of the wafer-level underfill for the manufacturing condition that corresponds to a temperature, a lighting condition, and/or an ambient gas composition.

3. The semiconductor device of claim 2 wherein the prefill material includes a nonconductive paste (NCP).

4. The semiconductor device of claim 3 wherein the NCP includes a fluxing function or trait.

5. The semiconductor device of claim 3 wherein the NCP has a top surface that is coplanar with or above one or more top surfaces of the traces.

6. The semiconductor device of claim 2 further comprising a solder mask with a top surface that is coplanar with or below one or more top surfaces of the traces, wherein the solder mask is laterally adjacent to the prefill material.

7. The semiconductor device of claim 1 wherein the prefill material directly contacts the wafer-level underfill.

8. A method of manufacturing a semiconductor device, comprising:
providing a substrate including traces, wherein the traces protrude above a top surface of the substrate;
forming a prefill material over the substrate and between the traces based on applying a nonconductive paste (NCP) between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; and
attaching an interim structure to the substrate over the prefill material, wherein:
the interim structure includes:
a die having a bottom surface,
pillars protruding from the bottom surface of the die,
solder on distal ends of the pillars opposite the bottom surface, and
a wafer-level underfill between the die and the prefill material; and

attaching the interim structure includes reflowing the solder and the wafer-level underfill.

9. The method of claim 8 wherein applying the NCP includes applying the NCP including a fluxing function or trait.

10. The method of claim 8 wherein applying the NCP includes applying the NCP with a top surface of the NCP coplanar with or above top surfaces of the traces.

11. The method of claim 8 wherein:
applying the NCP includes applying the NCP directly contacting at least a portion of one or more top surfaces of the traces;
attaching the interim structure includes removing the NCP from at least a portion of one or more top surfaces of the traces based on a fluxing function associated with the NCP.

12. The method of claim 8 wherein attaching the interim structure includes attaching the interim structure without curing the NCP.

13. The method of claim 8 further comprising at least partially curing the NCP before attaching the interim structure.

14. The method of claim 8 further comprising assembling the interim structure including:
providing the die including the pillars extending from the bottom surface of the die;
forming solder bumps on the pillars opposite the die; and
laminating the wafer-level underfill directly contacting the bottom surface and pillars.

15. The method of claim 14 wherein reflowing the solder bumps and the wafer-level underfill includes reflowing the solder bumps to directly contact the traces and the pillars and reflowing the wafer-level underfill to directly contact the prefill material.

Assignees

• Micron Technology Inc

Inventors

• Luo Shijian
• Hacker Jonathan S

Classifications

• H01L2224/83191

  Electricity · mapped topic

• H01L2224/16227

  Electricity · mapped topic

• H01L2224/26145

  Electricity · mapped topic

• H01L2224/13082

  Electricity · mapped topic

• H01L2224/73204

  Electricity · mapped topic