Multi-layer ceramic capacitor and method of producing the same

Patent metadata

Field	Value
Publication number	US-10622152-B2
Application number	US-201715782412-A
Country	US
Kind code	B2
Filing date	Oct 12, 2017
Priority date	Oct 17, 2016
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

A multi-layer ceramic capacitor includes a multi-layer unit and a side margin. The multi-layer unit includes ceramic layers laminated in a first direction and internal electrodes disposed between the ceramic layers. The side margin covers the multi-layer unit from a second direction orthogonal to the first direction and has a porosity of 1% or less.

First claim

What is claimed is:

1. A multi-layer ceramic capacitor, comprising:
a multi-layer unit having a height measured in a first direction, a width measured in a second direction orthogonal to the first direction, and a length measured in a third direction orthogonal to the first direction and the second direction, the length being larger the height and the width, the multi-layer unit including
ceramic layers laminated in the first direction, and
internal electrodes disposed between the ceramic layers; and

a side margin that covers the multi-layer unit from the second direction and has a porosity of 1% or less,
wherein a dimension of the side margin in the second direction is 5 μm or more and 15 μm or less,
wherein the multi-layer unit further includes a cover disposed on the internal electrodes, a dimension of the cover in the first direction being larger than the dimension of the side margin in the second direction, and
wherein each of the internal electrodes includes an oxidized area, the oxidized area being adjacent to the side margin and having a dimension in the second direction that is 0.4 μm or more.

2. The multi-layer ceramic capacitor according to claim 1 , wherein
the dimension of the side margin in the second direction is 10 μm or less.

3. A method of producing a multi-layer ceramic capacitor, comprising:
producing an unsintered multi-layer chip having a height measured in a first direction, a width measured in a second direction orthogonal to the first direction, and a length measured in a third direction orthogonal to the first direction and the second direction, the length being larger the height and the width, the multi-layer unit including
a capacitance forming unit including
ceramic layers laminated in the first direction, and
internal electrodes disposed between the ceramic layers, and

a cover that is made of insulating ceramics and covers the capacitance forming unit from the first direction;

producing an unsintered body by covering the unsintered multi-layer chip by a side margin made of insulating ceramics from the second direction; and
producing a body by sintering the unsintered body, the side margin of the body after subjected to the sintering having a porosity of 1% or less,
wherein a dimension of the cover in the first direction is larger than the dimension of the side margin in the second direction, a dimension of the side margin in the second direction being 5 μm or more and 15 μm or less after the sintering of the unsintered body, and
wherein each of the internal electrodes includes an oxidized area, the oxidized area being adjacent to the side margin and having a dimension in the second direction that is 0.4 μm or more.

4. The method of producing a multi-layer ceramic capacitor according to claim 3 , wherein
the multi-layer chip punches out a side margin sheet mainly made of insulating ceramics, to cover the unsintered body with the side margin.

5. The method of producing a multi-layer ceramic capacitor according to claim 3 , wherein
the unsintered body is subjected to hydrostatic pressing.

6. The method of producing a multi-layer ceramic capacitor according to claim 3 , wherein
the unsintered body is subjected to debinder processing, and
ceramics is deposited on the side margin subjected to the debinder processing.

7. The method of producing a multi-layer ceramic capacitor according to claim 6 , wherein
powder of ceramics is sprayed on the side margin subjected to the debinder processing.

8. The method of producing a multi-layer ceramic capacitor according to claim 6 , wherein
ceramics is spattered on the side margin subjected to the debinder processing.

9. The method of producing a multi-layer ceramic capacitor according to claim 6 , wherein
ceramics is vacuum-deposited on the side margin subjected to the debinder processing.

Assignees

• Taiyo Yuden Kk

Inventors

• Kogure Toshimitsu
• Kobayashi Joji
• Kato Yasunari
• Sato Yosuke
• Fukuoka Tetsuhiko
• Ono Ryo

Classifications

• H01G4/12 Primary

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

• H01G4/012 Primary

  Form of non-self-supporting electrodes · CPC title

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/224

  Housing; Encapsulation · CPC title

• H01G4/01

  Form of self-supporting electrodes · CPC title