Capacitor and method for manufacturing same
US-2024347278-A1 · Oct 17, 2024 · US
Multilayer ceramic capacitor and board having the same
US2016196918A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016196918-A1 |
| Application number | US-201514877876-A |
| Country | US |
| Kind code | A1 |
| Filing date | Oct 7, 2015 |
| Priority date | Jan 6, 2015 |
| Publication date | Jul 7, 2016 |
| Grant date | — |
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Abstract
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A multilayer ceramic capacitor includes a ceramic body including an active portion including dielectric layers and internal electrodes that are alternately stacked and a margin portion disposed on outer surfaces of the active portion; and external electrodes disposed on outer surfaces of the ceramic body. The margin portion includes an inner half adjacent to the active portion and an outer half adjacent to the edge of the ceramic body, and a porosity of the inner half is greater than a porosity of the outer half.
First claim
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What is claimed is: 1 . A multilayer ceramic capacitor comprising: a ceramic body including an active portion including dielectric layers and internal electrodes that are alternately stacked and a margin portion disposed on outer surfaces of the active portion; and external electrodes disposed on outer surfaces of the ceramic body, wherein the margin portion includes an inner half adjacent to the active portion and an outer half adjacent to the edge of the ceramic body, and a porosity of the inner half is greater than a porosity of the outer half. 2 . The multilayer ceramic capacitor of claim 1 , wherein the porosity of the inner half is 0.06% to 2.0%, and the porosity of the outer half is 0.05% or less. 3 . The multilayer ceramic capacitor of claim 1 , wherein a size of each pore in the inner half is 0.05 μm to 0.1 μm. 4 . The multilayer ceramic capacitor of claim 1 , wherein a size of each pore in the outer half is 0.015 μm to 0.03 μm. 5 . The multilayer ceramic capacitor of claim 1 , wherein in margin portions disposed on upper and lower surfaces of the active portion, dielectric grains of the inner half and the outer half are different from each other. 6 . A board having a multilayer ceramic capacitor, comprising: a printed circuit board on which a plurality of electrode pads are disposed; and the multilayer ceramic capacitor installed on the printed circuit board, wherein the multilayer ceramic capacitor includes a ceramic body including an active portion including dielectric layers and internal electrodes that are alternately stacked and a margin portion disposed on outer surfaces of the active portion, and external electrodes disposed on outer surfaces of the ceramic body, and the margin portion includes an inner half adjacent to the active portion and an outer half adjacent to the edge of the ceramic body, and a porosity of the inner half is greater than a porosity of the outer half. 7 . The board having a multilayer ceramic capacitor of claim 6 , wherein the porosity of the inner half is 0.06% to 2.0%, and the porosity of the outer half is 0.05% or less. 8 . The board having a multilayer ceramic capacitor of claim 6 , wherein a size of each pore in the inner half is 0.05 μm to 0.1 μm. 9 . The board having a multilayer ceramic capacitor of claim 6 , wherein a size of each pore in the outer half is 0.015 μm to 0.03 μm. 10 . The board having a multilayer ceramic capacitor of claim 6 , wherein in margin portions disposed on upper and lower surfaces of the active portion, sizes of dielectric grains of the inner half and the outer half are different from each other.
Assignees
Inventors
Classifications
based on alkaline earth titanates · CPC title
Non-printed capacitor · CPC title
- H01G4/30Primary
Stacked capacitors (H01G4/33 takes precedence) · CPC title
- H01G4/1209Primary
characterised by the ceramic dielectric material (H01G4/1272, H01G4/1281 take precedence) · CPC title
electrically connecting two or more layers of a stacked or rolled capacitor · CPC title
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- What does patent US2016196918A1 cover?
- A multilayer ceramic capacitor includes a ceramic body including an active portion including dielectric layers and internal electrodes that are alternately stacked and a margin portion disposed on outer surfaces of the active portion; and external electrodes disposed on outer surfaces of the ceramic body. The margin portion includes an inner half adjacent to the active portion and an outer half…
- Who is the assignee on this patent?
- Samsung Electro Mech
- What technology area does this patent fall under?
- Primary CPC classification H01G4/30. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Jul 07 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).