Instruction prefetch halting upon predecoding predetermined instruction types

Patent metadata

Field	Value
Publication number	US-10620953-B2
Application number	US-201715432121-A
Country	US
Kind code	B2
Filing date	Feb 14, 2017
Priority date	Mar 31, 2016
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

A data processing apparatus has prefetch circuitry for prefetching instructions from a data store into an instruction queue. Branch prediction circuitry is provided for predicting outcomes of branch instructions and the prefetch circuitry may prefetch instructions subsequent to the branch based on the predicted outcome. Instruction identifying circuitry identifies whether a given instruction prefetched from the data store is a predetermined type of program flow altering instruction and if so then controls the prefetch circuitry to halt prefetching of subsequent instructions into the instruction queue.

First claim

We claim:

1. A data processing apparatus comprising:
prefetch circuitry to prefetch instructions from a data store into an instruction queue;
processing circuitry to perform data processing in response to instructions from the instruction queue;
branch prediction circuitry to predict an outcome or target of a branch instruction, wherein the prefetch circuitry is configured to prefetch instructions subsequent to the branch instruction selected in dependence on the predicted outcome or target of the branch instruction; and
instruction identifying circuitry to identify whether a given instruction prefetched from the data store is a predetermined type of program flow altering instruction comprising an arithmetic instruction, logical instruction, load instruction or register move instruction specifying a program counter register as a destination register, and in response to identifying that the given instruction is said predetermined type of program flow altering instruction, to control the prefetch circuitry to halt prefetching of instructions subsequent to said predetermined type of program flow altering instruction into the instruction queue;
wherein the predetermined type of program flow altering instruction comprises a non-branch instruction for which branch prediction by the branch prediction circuitry is omitted.

2. The data processing apparatus according to claim 1 , wherein the prefetch circuitry is configured to resume prefetching of instructions subsequent to said predetermined type of program flow altering instruction into the instruction queue in response to an indication of a resolved outcome or target of the predetermined type of program flow altering instruction received from the processing circuitry.

3. The data processing apparatus according to claim 1 , wherein the branch instruction comprises an opcode identifying that the instruction is a branch instruction.

4. The data processing apparatus according to claim 1 , wherein the predetermined type of program flow altering instruction comprises at least one type of instruction for which the instruction identifying circuitry is configured to identify whether the instruction is a program flow altering instruction in dependence on at least one parameter of the instruction other than an opcode.

5. The data processing apparatus according to claim 1 , wherein in response to a program-counter-relative load instruction identifying an offset amount, the processing circuitry is configured to load into a destination register a data value having an address offset from an instruction address of the program-counter-relative load instruction by the offset amount.

6. The data processing apparatus according to claim 1 , wherein the instruction identifying circuitry is configured to identify whether the given instruction is a privilege-level changing instruction for redirecting program flow to a process having a different privilege level to a current process, and in response to identifying that the given instruction is said privilege-level changing instruction, to control the prefetch circuitry to halt prefetching of instructions subsequent to said privilege-level changing instruction into the instruction queue.

7. The data processing apparatus according to claim 1 , wherein the instruction identifying circuitry is configured to identify whether the given instruction is a wait-for-exception instruction for triggering the processing circuitry to pause processing until an exception event is detected, and in response to identifying that the given instruction is said wait-for-exception instruction, to control the prefetch circuitry to halt prefetching of instructions subsequent to said wait-for-exception instruction into the instruction queue.

8. The data processing apparatus according to claim 1 , wherein the instruction identifying circuitry is configured to identify whether the given instruction is a context synchronization instruction for triggering a flush of pending instructions subsequent to the context synchronization instruction from the processing circuitry and the prefetch circuitry, and in response to identifying that the given instruction is said context synchronization instruction, to control the prefetch circuitry to halt prefetching of instructions subsequent to said context synchronization instruction into the instruction queue.

9. The data processing apparatus according to claim 8 , wherein in response to a function call branch instruction specifying a target address, the prefetch circuitry is configured to store a return address to a call/return data structure, and the prefetch circuitry is configured to prefetch a subsequent instruction identified by the target address into the instruction queue; and
in response to a function return branch instruction, the prefetch circuitry is configured to prefetch into the instruction queue a subsequent instruction identified by the return address read from the call/return data structure.

10. A data processing apparatus comprising:
means for prefetching instructions from a data store into an instruction queue;
means for performing data processing in response to instructions from the instruction queue;
means for predicting an outcome or target of a branch instruction, wherein the means for prefetching is configured to prefetch instructions subsequent to the branch instruction selected in dependence on the predicted outcome of the branch instruction; and
means for identifying whether a given instruction prefetched from the data store is a predetermined type of program flow altering instruction comprising an arithmetic instruction, logical instruction, load instruction or register move instruction specifying a program counter register as a destination register, and in response to identifying that the given instruction is said predetermined type of program flow altering instruction, controlling the means for prefetching to halt prefetching of instructions subsequent to said predetermined type of program flow altering instruction into the instruction queue;
wherein the predetermined type of program flow altering instruction comprises a non-branch instruction for which branch prediction by the branch prediction circuitry is omitted.

11. A data processing method comprising:
prefetching instructions from a data store into an instruction queue; and
performing data processing in response to instructions from the instruction queue;
wherein the prefetching comprises:
prefetching instructions subsequent to a branch instruction selected in dependence on a predicted outcome or target of the branch instruction; and
identifying whether a given instruction prefetched from the data store is a predetermined type of program flow altering instruction comprising an arithmetic instruction, logical instruction, load instruction or register move instruction specifying a program counter register as a destination register, and in response to identifying that the given instruction is said predetermined type of program flow altering instruction, halting prefetching of instructions subsequent to said predetermined type of program flow altering instruction into the instruction queue;
wherein the predetermined type of program flow altering instruction comprises a non-branch instruction for which branch prediction by the branch prediction circuitry is omitted.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Johar Kauser Yakub
• Penton Antony John

Classifications

• G06F9/3867

  using instruction pipelines · CPC title

• G06F9/3804 Primary

  for branches, e.g. hedging, branch folding · CPC title

• G06F9/324

  using program counter relative addressing · CPC title

• G06F9/3806

  using address prediction, e.g. return stack, branch history buffer · CPC title

• G06F9/3005 Primary

  to perform operations for flow control · CPC title