Dynamic memory for compute resources in a data center

US10616669B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10616669-B2
Application numberUS-201715476915-A
CountryUS
Kind codeB2
Filing dateMar 31, 2017
Priority dateJul 22, 2016
Publication dateApr 7, 2020
Grant dateApr 7, 2020

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Examples may include sleds for a rack in a data center including physical compute resources and memory for the physical compute resources. The memory can be disaggregated, or organized into first level and second level memory. A first sled can comprise the physical compute resources and a first set of physical memory resources while a second sled can comprise a second set of physical memory resources. The first set of physical memory resources can be coupled to the physical compute resources via a local interface while the second set of physical memory resources can be coupled to the physical compute resources via a fabric.

First claim

Opening claim text (preview).

The invention claimed is: 1. A system for a data center comprising: a rack comprising a plurality of sled spaces; at least two or more compute sleds coupled to the rack via at least two or more of the plurality of sled spaces, each of the two or more compute sleds comprising: at least one physical compute resource; a set of physical first level memory resources coupled to the at least one physical compute resource; a first compute sled memory controller to couple the at least one physical compute resource to the set of physical first level memory resources; a second compute sled memory controller to couple the at least one physical compute resource to a portion of a set of physical second level memory resources; and a compute sled fabric interface to couple to a fabric; and a memory resource sled coupled to the rack via another one of the plurality of sled spaces different than the two or more of the plurality of sled spaces, the memory resource sled comprising: the set of physical second level memory resources; and a second level memory sled fabric interface to couple, to each of the at least one physical compute resources of the two or more compute sleds via the fabric and the compute sled fabric interfaces, a portion of the set of physical second level memory resources, the portion of the set of physical second level memory resources coupled to a first one of the at least two or more compute sleds different than the portion of the set of physical second level memory resources coupled to a second one of the at least two or more compute sleds. 2. The system of claim 1 , the sets of physical first level memory resources comprising volatile memory. 3. The system of claim 2 , the set of physical second level memory resources comprising byte-addressable write-in place nonvolatile memory. 4. The system of claim 1 , each of the at least one physical compute resources comprising a central processing unit, a field programmable gate array, a graphics processing unit, or an application specific integrated circuit. 5. The system of claim 1 , the at least one physical compute resource of each of the two or more compute sleds coupled to the set of physical first level memory resources via a local interface, the local interface a peripheral component interconnect express compliant standard interface. 6. The system of claim 1 , the fabric an optical fabric. 7. The system of claim 1 , comprising a virtual infrastructure management framework to dynamically allocate the portions of the physical second level memory resources to each of the two or more compute sleds. 8. The system of claim 1 , wherein the portion of the set of physical second level memory resources coupled to the first one of the at least two or more compute sleds to be dynamically adjusted based on a workload to be executed on the at least one physical compute resource of the first one of the at least two or more compute sleds. 9. An apparatus for a compute resource sled of a data center, comprising: at least one physical compute resource; a set of physical first level memory resources coupled to the at least one physical compute resource; a first compute sled memory controller to couple the at least one physical compute resource to the set of physical first level memory resources; a fabric interface, the fabric interface to couple the at least one physical compute resource to a portion of a set of physical second level memory resources via a fabric, the set of physical second level memory resources to be shared between the compute resource sled and another compute resource sled of the data center; and a second compute sled memory controller to couple the at least one physical compute resource to the portion of the set of physical second level memory resources, the portion of the set of physical second level memory resources coupled to the compute resource sled of the data center different than the portion of the set of physical second level memory resources coupled to the other compute resource sled of the data center. 10. The apparatus of claim 9 , the first set of physical memory resources comprising volatile memory. 11. The apparatus of claim 10 , the second set of physical memory resources comprising three-dimensional (3D) cross-point memory. 12. The apparatus of claim 9 , the at least one physical compute resource comprising a central processing unit, a field programmable gate array, a graphics processing unit, or an application specific integrated circuit. 13. The apparatus of claim 9 , the at least one physical compute resource coupled to the set of physical first level memory resources via a local interface, the local interface a peripheral component interconnect express compliant standard interface. 14. The apparatus of claim 9 , the fabric an optical fabric. 15. The apparatus of claim 9 , wherein the portion of the set of physical second level memory resources coupled to the compute resource sled of the data center to be dynamically adjusted based on a workload to be executed on the at least one physical compute resource of the compute resource sled of the data center. 16. A method comprising: allocating a first portion of a set of physical second level memory resources to a first one of a plurality of compute sleds; allocating a second portion of the set of physical second level memory resources, different than the first portion of the set of physical second level memory resources, to a second one of the plurality of compute sleds; coupling, via a fabric, at least one physical compute resource of the first one of the plurality of compute sleds to the first portion of the set of physical second level memory resources; and coupling, via the fabric, at least one physical compute resource of the second one of the plurality of compute sleds to the second portion of the set of physical second level memory resources, wherein each compute sled of the plurality of compute sleds comprise: a first compute sled memory controller to couple the at least one physical compute resource of the compute sled to a set of physical first level memory resources of the compute sled, a fabric interface to couple the at least one physical compute resource of the compute sled to the respective portion of the set of physical second level memory resources via the optical fabric, and a second compute sled memory controller to couple the at least one physical compute resource of the compute sled to the respective portion of the set of physical second level memory resources. 17. The method of claim 16 , the set of physical second level memory resources comprising three-dimensional (3D) cross-point memory. 18. The method of claim 16 , the at least one physical compute resource comprising a central processing unit, a field programmable gate array, a graphics processing unit, or an application specific integrated circuit. 19. The method of claim 16 , comprising: composing a first virtual compute platform from the at least one physical compute resource of the first compute sled and the first portion of the set of physical second level memory resources; and allocating the first portion of the set of physical second level memory resources to the first compute sled based on a workload to be executed by the first virtual compute platform. 20. The method of claim 19 , comprising: composing a second virtual compute platform from the at least one physical compute resource of the second compute sled and the second portion of the set of physical second level memory resources; and

Assignees

Inventors

Classifications

  • G06F15/161Primary

    Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning (casings, cabinets, racks or drawers for data centers H05K5/00) · CPC title

  • Hierarchical allocation of resources, e.g. involving a hierarchy of local and centralised entities · CPC title

  • Provisions for forwarding or routing, e.g. lookup tables · CPC title

  • Ensuring fulfilment of SLA · CPC title

  • Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10616669B2 cover?
Examples may include sleds for a rack in a data center including physical compute resources and memory for the physical compute resources. The memory can be disaggregated, or organized into first level and second level memory. A first sled can comprise the physical compute resources and a first set of physical memory resources while a second sled can comprise a second set of physical memory res…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06F15/161. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 07 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).