Electronic system with memory network mechanism and method of operation thereof

US2016006808A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016006808-A1
Application numberUS-201514631118-A
CountryUS
Kind codeA1
Filing dateFeb 25, 2015
Priority dateJul 7, 2014
Publication dateJan 7, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic system includes: a network; a memory device, coupled to the network; a host processor, coupled to the network and the memory device, providing a transaction protocol including cut through.

First claim

Opening claim text (preview).

What is claimed is: 1 . An electronic system comprising: a network; a memory device, coupled to the network; a host processor, coupled to the network and the memory device, providing a transaction protocol including cut through. 2 . The system as claimed in claim 1 further comprising a compute route node, coupled to the network, for the transaction protocol. 3 . The system as claimed in claim 1 further comprising a memory route node, coupled to the network, for the transaction protocol. 4 . The system as claimed in claim 1 wherein the network includes a memory transaction for transfer with the transaction protocol including cut through. 5 . The system as claimed in claim 1 wherein the network includes a memory transaction for access on the network. 6 . The system as claimed in claim 1 wherein the network includes a packet for transfer with the transaction protocol including cut through. 7 . The system as claimed in claim 1 wherein the network includes a packet for access on the network. 8 . The system as claimed in claim 1 wherein the network includes a start section for starting the transaction protocol. 9 . The system as claimed in claim 1 wherein the network includes an end section for ending the transaction protocol. 10 . The system as claimed in claim 1 further comprising a route device, coupled to the network, for providing access to the memory. 11 . A method of operation of an electronic system comprising: providing a network; accessing a memory, coupled to the network; connecting a processor, coupled to the network and the memory, for providing a transaction protocol with cut through. 12 . The method as claimed in claim 11 further comprising providing a compute route node, coupled to the network, for the transaction protocol. 13 . The method as claimed in claim 11 further comprising providing a memory route node, coupled to the network, for the transaction protocol. 14 . The method as claimed in claim 11 further comprising providing a memory transaction for transfer with the transaction protocol including cut through. 15 . The method as claimed in claim 11 further comprising providing a memory transaction for access on the network. 16 . The method as claimed in claim 11 further comprising providing a packet, coupled for transfer with the transaction protocol including cut through. 17 . The method as claimed in claim 11 further comprising providing a packet for access on the network. 18 . The method as claimed in claim 11 further comprising providing a start section for starting the transaction protocol. 19 . The method as claimed in claim 11 further comprising providing an end section for ending the transaction protocol. 20 . The method as claimed in claim 11 further comprising providing a route device, coupled to the network, for providing access to the memory.

Assignees

Inventors

Classifications

  • G06F3/067Primary

    Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title

  • Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

  • for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS] · CPC title

  • in relation to throughput · CPC title

  • H04L49/251Primary

    Cut-through or wormhole routing · CPC title

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Frequently asked questions

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What does patent US2016006808A1 cover?
An electronic system includes: a network; a memory device, coupled to the network; a host processor, coupled to the network and the memory device, providing a transaction protocol including cut through.
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/067. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Jan 07 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).