Digital to analog (DAC) converter with current calibration

Patent metadata

Field	Value
Publication number	US-9991900-B1
Application number	US-201715666738-A
Country	US
Kind code	B1
Filing date	Aug 2, 2017
Priority date	Aug 2, 2017
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A digital to analog converter convert digital data in binary format to thermometer bit vectors. A first set of the thermometer bit vectors corresponds to most significant bits of the digital data and a second set of the thermometer bit vectors corresponds to least significant bits of the digital data. Connections of first current sources corresponding to the first set of the thermometer bit vectors and second current sources corresponding to the second set of the thermometer bit vectors are dynamically and randomly alternated to a first output line and a second output line. Calibration current is applied to the second current sources so a total current of the second current sources and the calibration current is within a predetermined range of an average current of the first current sources.

First claim

What is claimed is:

1. A digital to analog converter (DAC) comprising:
a first sub-DAC configured to convert most significant bits (MSBs) of digital input data, the first sub-DAC including:
a first array of current sources,
first dynamic element randomizer circuitry configured to generate a first randomly modified data vector from a first thermometer coded data vector derived from the digital input data, and
a first switch driver that controls coupling of the first array of current sources to a first output line or a second output line of the DAC based on the first randomly modified data vector;

a second sub-DAC configured to convert at least some least significant bits (LSBs) of the digital input data, the second sub-DAC including:
a second array of current sources including a calibration current source,
second dynamic element randomizer circuitry configured to generate a second randomly modified data vector from a second thermometer coded data vector derived from the digital input data, and
a second switch driver that controls coupling of the second array of current sources to the first output line or the second output line of the DAC based on the second randomly modified data vector;

a first binary to thermometer decoder configured to convert the MSBs of digital input data from binary format to the first thermometer coded data vector;
a second binary to thermometer decoder configured to convert the at least some LSBs of digital input data from binary format to the second thermometer coded data vector.

2. A digital to analog converter (DAC) comprising:
a first sub-DAC configured to convert most significant bits (MSBs) of digital input data, the first sub-DAC including:
a first array of current sources,
first dynamic element randomizer circuitry configured to generate a first randomly modified data vector from a first thermometer coded data vector derived from the digital input data, and
a first switch driver that controls coupling of the first array of current sources to a first output line or a second output line of the DAC based on the first randomly modified data vector;

a second sub-DAC configured to convert at least some least significant bits (LSBs) of the digital input data, the second sub-DAC including:
a second array of current sources including a calibration current source,
second dynamic element randomizer circuitry configured to generate a second randomly modified data vector from a second thermometer coded data vector derived from the digital input data, and
a second switch driver that controls coupling of the second array of current sources to the first output line or the second output line of the DAC based on the second randomly modified data vector;

a third sub-DAC configured to convert other LSBs that are not converted by the second sub-DAC, the third sub-DAC including:
a third array of current sources including a calibration current source,
second dynamic element randomizer circuitry configured to generate a third randomly modified data vector from a third thermometer coded data vector derived from the digital input data, and
a third switch driver that controls coupling of the third array of current sources to the first output line or the second output line of the DAC based on the third randomly modified data vector.

3. The DAC of claim 2 further comprising:
a third binary to thermometer decoder configured to convert the other LSBs of digital input data from binary format to the third thermometer coded data vector.

4. A digital to analog converter (DAC) comprising:
a first sub-DAC configured to convert most significant bits (MSBs) of digital input data, the first sub-DAC including:
a first array of current sources,
first dynamic element randomizer circuitry configured to generate a first randomly modified data vector from a first thermometer coded data vector derived from the digital input data, and
a first switch driver that controls coupling of the first array of current sources to a first output line or a second output line of the DAC based on the first randomly modified data vector;

a second sub-DAC configured to convert at least some least significant bits (LSBs) of the digital input data, the second sub-DAC including:
a second array of current sources including a calibration current source, second dynamic element randomizer circuitry configured to generate a second randomly modified data vector from a second thermometer coded data vector derived from the digital input data, and
a second switch driver that controls coupling of the second array of current sources to the first output line or the second output line of the DAC based on the second randomly modified data vector;

wherein the first array of current sources includes:
a first switch;
a second switch;
a current source for each bit of the MSBs, each current source for each bit in the MSBs including a first terminal connected to a first voltage supply (VDD) and a second terminal connected to a first terminal of the first switch and a first terminal of the second switch, wherein
the second terminal of the first switch is connected to the first output line,
the second terminal of the second switch is connected to the second output line, and
the first switch driver controls the first and second switches to couple the current source to the first output line or the second output line.

5. The DAC of claim 4 wherein the second array of current sources includes:
a first switch;
a second switch;
a current source for each bit of the at least some LSBs, each current source for each bit in the at least some LSBs including a first terminal connected to the first voltage supply (VDD) and a second terminal connected to a first terminal of the first switch and a first terminal of the second switch, wherein
the second terminal of the first switch is connected to the first output line,
the second terminal of the second switch is connected to the second output line, and
the second switch driver controls the first and second switches to couple the current source for each bit in the at least some LSBs to the first output line or the second output line.

6. The DAC of claim 2 wherein the third array of current sources includes:
a first switch;
a second switch;
a third switch;
at least two current sources for each bit in the other LSBs, a first current source of the at least two current sources for each bit in the other LSBs including a first terminal connected to a first voltage supply (VDD) and a second terminal connected to a first terminal of the first switch and a first terminal of the second switch, wherein
the second terminal of the first switch is connected to the first output line,
the second terminal of the second switch is connected to the second output line, and
the third switch driver controls the first and second switches to couple the current source for each bit in the other LSBs to the first output line or the second output line;
the calibration current circuitry includes a second current source of the at least two current sources for each bit in the other LSBs and includes a first terminal connected to the first voltage supply (VDD) and a second terminal connected to a first terminal of the third switch, a second terminal of the third switch is connected to the second terminal of the first current source;

a calibration controller configured to control the third switch to connect or disconnect the second terminal of the second current source to the second terminal of the first current source.

7. The DAC of claim 6 wherein:
the at least two current sources for each bit in the other LSBs provide less current than current sources in the first and second arrays of current sources.

8. A digital t

Assignees

• Nxp Usa Inc

Inventors

• Kabir Mohammad Nizam
• Hoseini Mariam
• Braswell Brandt

Classifications

• H03M1/0673

  using random selection of the elements (with data-controlled random generator H03M1/0665) · CPC title

• H03M1/1009 Primary

  Calibration · CPC title

• H03M1/742

  using current sources as quantisation value generators · CPC title

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title