High-linearity flash analog to digital converter

Patent metadata

Field	Value
Publication number	US-10615815-B2
Application number	US-201916400431-A
Country	US
Kind code	B2
Filing date	May 1, 2019
Priority date	May 2, 2018
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

An analog-to-digital converter circuit comprises code-shuffling circuitry, a plurality of digital-to-analog converter circuits, a plurality of difference circuits, and a plurality of latch circuits. The code-shuffling circuitry is operable to shuffle a plurality of digital codes among a plurality of its outputs. The plurality of digital-to-analog converter circuits are operable to convert a digital code on the respective one of the outputs to a corresponding one of a plurality of analog reference voltages. The plurality of difference circuits is operable to generate a respective one of a plurality of difference signals corresponding to a difference between an input voltage and a respective one of the plurality of reference voltages. The plurality of latch circuits is operable to latch a respective one of the plurality of difference signals to a corresponding one of a plurality of digital values.

First claim

What is claimed is:

1. A system comprising:
an analog-to-digital converter circuit comprising:
code-shuffling circuitry operable to shuffle, over time, a plurality of digital codes among a plurality of outputs of the code-shuffling circuitry;
a plurality of digital-to-analog converter circuits, each of which is
coupled to a respective one of the plurality of outputs of the code-shuffling circuitry; and
operable to convert a digital code on the respective one of the plurality of outputs to a corresponding one of a plurality of analog reference voltages;

a plurality of difference circuits, each of which is operable to generate a respective one of a plurality of difference signals corresponding to a difference between an input voltage and a respective one of the plurality of analog reference voltages; and
a plurality of latch circuits, each of which is operable to latch a respective one of the plurality of difference signals to a corresponding digital value.

2. The system of claim 1 , wherein each of the plurality of digital-to-analog converter circuits is coupled to the respective one of the plurality of outputs of the code-shuffling circuitry via a respective one of a plurality of sample and hold circuits.

3. The system of claim 1 , wherein each of the plurality of digital-to-analog converter circuits is a resistive digital-to-analog converter circuit.

4. The system of claim 1 , wherein one or more of the plurality of difference circuits is an active subtractor.

5. The system of claim 1 , wherein one or more of the plurality of difference circuits is a passive subtractor.

6. The system of claim 5 , wherein an output impedance of each of the plurality of digital-to-analog converter circuits is independent of a voltage at its input.

7. The system of claim 6 , wherein an output of each of the plurality of digital-to-analog converter circuits is shorted to an input of a respective one of the plurality of latch circuits via a determined impedance.

8. The system of claim 1 , comprising dynamic element matching circuitry operable to control the code-shuffling circuitry based on one or more outputs of the plurality of latch circuits.

9. The system of claim 1 , wherein the code-shuffling circuitry is operable to shuffle the plurality of digital codes periodically.

10. The system of claim 1 , wherein an output of the analog-to-digital converter circuit is feedback via a thermometric feedback digital-to-analog converter.

11. A method comprising:
shuffling over time, by code-shuffling circuitry of an analog-to-digital converter, a plurality of digital codes among a plurality of outputs of the code-shuffling circuitry;
converting, a plurality of digital-to-analog converter circuits of the analog-to-digital converter, the plurality of digital codes on the plurality of outputs of the code-shuffling circuitry to a plurality of analog reference voltages;
generating, by a plurality of difference circuits, a plurality of difference signals, each of which corresponds to a difference between an input voltage and a respective one of the plurality of analog reference voltages; and
latching, by a plurality of latch circuits, the plurality of difference signals to a corresponding plurality of digital values.

12. The method of claim 11 , wherein the plurality of digital-to-analog converter circuits receive the plurality of digital codes on the plurality of outputs of the code-shuffling circuitry via a plurality of sample-and-hold circuits.

13. The method of claim 11 , wherein each of the plurality of digital-to-analog converter circuits is a resistive digital-to-analog converter circuit.

14. The method of claim 11 , wherein one or more of the plurality of difference circuits is an active subtractor.

15. The method of claim 11 , wherein one or more of the plurality of difference circuits is a passive subtractor.

16. The method of claim 15 , wherein an output impedance of each of the plurality of digital-to-analog converter circuits is independent of a voltage at its input.

17. The method of claim 16 , wherein an output of each of the plurality of digital-to-analog converter circuits is shorted to an input of a respective one of the plurality of latch circuits via a determined impedance.

18. The method of claim 11 , comprising controlling, via dynamic element matching circuitry, the code-shuffling circuitry based on one or more outputs of the plurality of latch circuits.

19. The method of claim 11 , wherein the shuffling over time of the plurality of digital codes comprises periodically shuffling.

20. The method of claim 11 , comprising converting, by a feedback digital-to-analog converter, an output of the analog-to-digital conversion circuit to an analog signal.

Assignees

• Maxliner Inc
• Maxlinear Inc

Inventors

• Mathur Rishi
• Debnath Chandrajit
• Ghosh Abhishek
• Pappu Anand Mohan

Classifications

• H03M1/361 Primary

  having a separate comparator and reference value for each quantisation level, i.e. full flash converter type · CPC title

• H03M1/066

  by continuously permuting the elements used, i.e. dynamic element matching · CPC title

• H03M3/338

  by permutation in the time domain, e.g. dynamic element matching (in multiple bit sub-converters H03M1/066) · CPC title