Process for creating a high density magnetic tunnel junction array test platform

Patent metadata

Field	Value
Publication number	US-10615337-B2
Application number	US-201916388774-A
Country	US
Kind code	B2
Filing date	Apr 18, 2019
Priority date	May 30, 2018
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

A method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. The method includes receiving a wafer having a plurality of bit cells arranged in a grid and etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. The method further includes fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell. The wafer is then planarized. The method further includes etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, and outputting the wafer for subsequent testing.

First claim

What is claimed is:

1. A device, comprising:
a grid of bit cells having a first density;
an array of pillars fabricated on a centrally located bit cell having a second density that is higher than the first density;
a bottom electrode layer comprising a plurality of bottom electrode traces connecting each of the memory cell pillars to a respective one of the grid of bit cells in a first fanout pattern; and
a top electrode layer comprising a plurality of top electrode traces connecting each of the memory cell pillars to a respective one of the grid of bit cells in a second fanout pattern.

2. The device of claim 1 , wherein the plurality of top electrode traces connect to the bit cells in the grid using vias.

3. The device of claims 1 , further comprising an array of metal posts located on top of the plurality of bottom electrode traces and operable to function as a base for the array of memory cell pillars.

4. The device of claim 1 , wherein each of the plurality of bottom electrode traces comprises tantalum nitride.

5. The device of claim 1 , wherein each of the plurality of top electrode traces comprises tantalum nitride.

6. The device of claim 1 , wherein each of the grid of bit cells further comprises a CMOS driving transistor for individually addressing each of the memory cell pillars.

7. The device of claim 1 , further comprising a silicon oxide passivation layer on the surface of the device.

8. A device, comprising:
a grid of bit cells having a first density;
an array of memory cell pillars fabricated on a centrally located bit cell having a second density that is higher than the first density;
a bottom electrode layer comprising of a plurality of bottom electrode traces connecting each of the memory cell pillars to a respective one of the grid of bit cells in a first fanout pattern;
a top electrode layer comprising a plurality of top electrode traces connecting each of the memory cell pillars to a respective one of the grid of bit cells in a second fanout pattern; and
a silicon oxide passivation layer on the surface of the device.

9. The device of claim 8 , wherein the plurality of top electrode traces connect to the bit cells in the grid using vias.

10. The device of claim 8 , further comprising an array of metal posts located on top of the plurality of bottom electrode traces and function as a base for the array of memory cell pillars.

11. The device of claim 8 , wherein each of the plurality of bottom electrode traces comprises tantalum nitride.

12. The device of claim 8 , wherein each of the plurality of top electrode traces comprises tantalum nitride.

13. The device of claim 8 , wherein each of the grid of bit cells further comprises a CMOS driving transistor for individually addressing each of the memory cell pillars.

14. A device, comprising:
a grid of bit cells having a first density;
an array of memory cell pillars fabricated on a centrally located bit cell having a second density that is higher than the first density;
a bottom electrode layer comprising a plurality of bottom electrode traces connecting each of the memory cell pillars to a respective one of the grid of bit cells in a first fanout pattern;
a top electrode layer comprising a plurality of top electrode traces connecting each of the memory cell to a respective one of the grid of bit cells in a second fanout pattern; and
a CMOS driving transistor for individually addressing each of the memory cell pillars.

15. The device of claim 14 , wherein the plurality of top electrode traces connect to the bit cells in the grid using vias.

16. The device of claim 14 , wherein an array of metal posts are located on top of the plurality of bottom electrode traces and function as a base for the array of memory cell pillars.

17. The device of claim 14 , wherein each of the plurality of bottom electrode traces comprises tantalum nitride.

18. The device of claim 14 , wherein each of the plurality of top electrode traces comprises tantalum nitride.

19. The device of claim 14 , further comprising a silicon oxide passivation layer on the surface of the device.

20. The device of claim 14 , further comprising a plurality of contact points operable to interface with a CMOS testing device.

21. The device of claim 14 , wherein the device comprises a pillar array test device.

22. The device of claim 14 , wherein the memory cell pillars comprise magnetic tunnel junction pillars.

23. The device of claim 1 , wherein the memory cell pillars comprise magnetic tunnel junction pillars.

24. The device of claim 8 , wherein the memory cell pillars comprise magnetic tunnel junction pillars.

Assignees

• Spin Memory Inc

Inventors

• Manandhar Pradeep
• Shrivastava Prachi
• Pinarbasi Mustafa
• Boone Thomas

Classifications

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H01L21/31051

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic