Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method

Patent metadata

Field	Value
Publication number	US-10615071-B2
Application number	US-201715664157-A
Country	US
Kind code	B2
Filing date	Jul 31, 2017
Priority date	Oct 24, 2014
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a buried oxide layer, a deep trench extending through the device layer, a dielectric filler in the deep trench, via holes in the dielectric filler, and conductive fillers in the via holes being the isolated deep substrate vias. The dielectric filler may include silicon oxide. The conductive fillers may include tungsten or copper. An adjacent pair of the isolated deep substrate vias within the deep trench has a pitch equal to or less than 1.0 microns.

First claim

The invention claimed is:

1. A method for forming a plurality of isolated deep substrate vias, said method comprising:
forming a buried oxide layer over a bulk semiconductor layer, and a device layer over said buried oxide layer;
forming a semiconductor device at an upper surface of the device layer, wherein the buried oxide layer is located at a lower surface of the device layer;
forming an isolation region in the device layer, wherein the isolation region electrically isolates the semiconductor device in the device layer; then
forming an insulative layer over the semiconductor device and the isolation region;
forming a deep trench extending through said insulative layer, said isolation region and said device layer, wherein the deep trench is formed starting from the insulative layer and proceeding to the lower surface of the device layer;
forming a dielectric filler in said deep trench, wherein the dielectric filler completely fills said deep trench;
forming a plurality of via holes through said dielectric filler;
forming a conductive filler in each of said via holes to form said plurality of isolated deep substrate vias;
removing said bulk semiconductor layer; and
exposing said isolated deep substrate vias through the buried oxide layer.

2. The method of claim 1 wherein said deep trench extends through said device layer and terminates on a top surface of said buried oxide layer.

3. The method of claim 1 wherein said via holes extend through said dielectric filler and said buried oxide layer.

4. The method of claim 1 wherein an adjacent pair of said isolated deep substrate vias within said deep trench has a pitch equal to or less than 1.0 microns.

5. The method of claim 1 further comprising forming a dielectric liner in each of said via holes prior to forming the conductive filler in each of said via holes.

6. The method of claim 1 , further comprising:
forming a first dielectric liner in said deep trench prior to forming the dielectric filler in said deep trench; and
forming a second dielectric liner in said via holes prior to forming the conductive filler in each of said via holes.

7. The method of claim 6 , wherein the dielectric filler, first dielectric liner and buried oxide layer have substantially similar compositions.

8. The method of claim 7 , wherein the dielectric filler comprises silicon oxide, the first dielectric liner comprises tetraethylorthosilicate (TEOS) and the buried oxide layer comprises silicon oxide.

9. The method of claim 1 , further comprising forming a dielectric liner in said deep trench before forming said dielectric filler in said deep trench.

10. The method of claim 1 , wherein the device layer is silicon having a thickness of at least 1.0 microns.

11. The method of claim 1 , wherein each of said isolated deep substrate vias has an aspect ratio equal to or greater than 5:1.

12. The method of claim 1 wherein said deep trench extends through said device layer and partially through said buried oxide layer.

Assignees

• Newport Fab Llc

Inventors

• Kar-Roy Arjun
• Howard David J

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/218

  in silicon-on-insulator [SOI] wafers · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H01L23/485

  Electricity · mapped topic