Vertical 3D memory device and accessing method
US-11877457-B2 · Jan 16, 2024 · US
US8976591B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8976591-B2 |
| Application number | US-201213619118-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 14, 2012 |
| Priority date | Jan 4, 2012 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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According to example embodiments, a nonvolatile memory device includes a first and a second NAND string. The first NAND string includes a first string selection transistor, a first local ground and a first global ground selection transistor, and first memory cells stacked in a direction perpendicular to a substrate. The second NAND string includes a second string selection transistor, a second local ground and a second global ground selection transistor, and second memory cells stacked in the direction perpendicular to the substrate. The device includes a selection line driver including path transistors configured to select and provide at least one operation voltage to the first and second string selection transistors, the first and second local and global ground selection transistors. The first and second string selection transistors are electrically isolated from each other, and the first and second global ground selection transistors are electrically connected.
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What is claimed is: 1. A nonvolatile memory device comprising: a first NAND string including a first string selection transistor, a first local ground selection transistor, a first global ground selection transistor, and a plurality of first memory cells stacked in a direction perpendicular to a substrate; a second NAND string including a second string selection transistor, a second local ground selection transistor, a second global ground selection transistor, and a plurality o…
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