Nonvolatile memory device and memory system including the same

US8976591B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8976591-B2
Application numberUS-201213619118-A
CountryUS
Kind codeB2
Filing dateSep 14, 2012
Priority dateJan 4, 2012
Publication dateMar 10, 2015
Grant dateMar 10, 2015

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Abstract

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According to example embodiments, a nonvolatile memory device includes a first and a second NAND string. The first NAND string includes a first string selection transistor, a first local ground and a first global ground selection transistor, and first memory cells stacked in a direction perpendicular to a substrate. The second NAND string includes a second string selection transistor, a second local ground and a second global ground selection transistor, and second memory cells stacked in the direction perpendicular to the substrate. The device includes a selection line driver including path transistors configured to select and provide at least one operation voltage to the first and second string selection transistors, the first and second local and global ground selection transistors. The first and second string selection transistors are electrically isolated from each other, and the first and second global ground selection transistors are electrically connected.

First claim

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What is claimed is: 1. A nonvolatile memory device comprising: a first NAND string including a first string selection transistor, a first local ground selection transistor, a first global ground selection transistor, and a plurality of first memory cells stacked in a direction perpendicular to a substrate; a second NAND string including a second string selection transistor, a second local ground selection transistor, a second global ground selection transistor, and a plurality o…

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What does patent US8976591B2 cover?
According to example embodiments, a nonvolatile memory device includes a first and a second NAND string. The first NAND string includes a first string selection transistor, a first local ground and a first global ground selection transistor, and first memory cells stacked in a direction perpendicular to a substrate. The second NAND string includes a second string selection transistor, a second …
Who is the assignee on this patent?
Nam Sang-Wan, Kang Kyung-Hwa, Park Junghoon, and 1 more
What technology area does this patent fall under?
Primary CPC classification G11C16/04. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).