Method for forming vertical field effect transistor devices having alternating drift regions and compensation regions

Patent metadata

Field	Value
Publication number	US-10608103-B2
Application number	US-201816226504-A
Country	US
Kind code	B2
Filing date	Dec 19, 2018
Priority date	Sep 23, 2015
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

A method for forming a semiconductor device includes forming a body implant region of a vertical field effect transistor arrangement in a semiconductor substrate and forming a plurality of compensation regions in the semiconductor substrate after forming the body implant region of the vertical field effect transistor arrangement. Further embodiments of methods for forming a semiconductor device are described.

First claim

What is claimed is:

1. A method for forming a semiconductor device, the method comprising:
forming a body implant region of a vertical field effect transistor arrangement in a semiconductor substrate;
forming a plurality of compensation regions in the semiconductor substrate after forming the body implant region of the vertical field effect transistor arrangement;
forming a first doping implant region of the vertical field effect transistor arrangement in the semiconductor substrate before forming the plurality of compensation regions in the semiconductor substrate; and
forming an electrically conductive contact structure which forms a short circuit connection between a part of the first doping implant region of the vertical field effect transistor arrangement and a part of the body implant region of the vertical field effect transistor arrangement.

2. The method of claim 1 , wherein forming the electrically conductive contact structure comprises forming a contact trench of the vertical field effect transistor arrangement in the semiconductor substrate, the electrically conductive contact structure being in contact with the first doping implant region of the vertical field effect transistor arrangement and the body implant region of the vertical field effect transistor arrangement within the contact trench of the vertical field effect transistor arrangement.

3. The method of claim 1 , wherein forming the plurality of compensation regions in the semiconductor substrate comprises:
forming a plurality of compensation trench structures in the semiconductor substrate; and
growing epitaxial semiconductor material in the plurality of compensation trench structures to form the plurality of compensation regions.

4. The method of claim 1 , further comprising performing an out-diffusion of the body implant region to form a body region of the vertical field effect transistor arrangement.

5. A method for forming a semiconductor device, the method comprising:
forming a plurality of compensation regions comprising semiconductor material within a plurality of compensation trench structures located in a semiconductor substrate; and
forming a plurality of self-aligned gate trench structures in portions of the plurality of compensation trench structures without semiconductor material.

6. The method of claim 5 , further comprising forming a plurality of gates of a vertical field effect transistor arrangement at sidewalls of the plurality of self-aligned gate trench structures.

7. The method of claim 5 , wherein forming the plurality of self-aligned gate trench structures in the portions of the plurality of compensation trench structures without semiconductor material comprises:
forming the plurality of self-aligned gate trench structures in unfilled portions of the plurality of compensation trench structures which remain unfilled after forming the plurality of compensation regions within the plurality of compensation trench structures.

8. The method of claim 7 , wherein forming the plurality of self-aligned gate trench structures in the unfilled portions of the plurality of compensation trench structures comprises:
etching sidewalls of the unfilled portions of the compensation trench structures so that the gate trench structures each have a lateral dimension larger than a lateral dimension of the compensation trench structures.

9. A method of forming a semiconductor device, the method comprising:
forming a plurality of drift regions of a vertical field effect transistor arrangement in a semiconductor substrate, the plurality of drift regions having a first conductivity type;
forming a plurality of compensation regions in the semiconductor substrate, the plurality of compensation regions having a second conductivity type, each drift region of the plurality of drift regions being arranged adjacent to at least one compensation region of the plurality of compensation regions;
forming a body region of a transistor structure of the vertical field effect transistor arrangement adjacent to a drift region of the plurality of drift regions; and
forming a gate trench structure in the semiconductor substrate, the gate trench structure comprising a gate extending substantially vertically along the body region of the transistor structure for controlling a substantially vertical channel region between a first doping region of the transistor structure and the drift region, at least part of the gate trench structure being located laterally between at least part of a first doping region contact structure in electrical connection with the first doping region of the transistor structure and at least part of a compensation region contact structure in electrical connection with the compensation region adjacent to the drift region of the transistor structure.

10. The method of claim 9 , wherein a contact resistance between the first doping region contact structure and the first doping region of the transistor structure is different from a contact resistance between the compensation region contact structure and the compensation region.

11. The method of claim 9 , wherein the compensation region contact structure is in contact with the compensation region within the gate trench structure.

12. The method of claim 9 , wherein the compensation region contact structure is laterally surrounded by at least part of the gate trench structure.

13. The method of claim 9 , further comprising forming an electrically conductive contact structure which forms a short circuit connection between a part of the first doping region of the transistor structure and a part of the body region of the transistor structure.

14. The method of claim 13 , wherein forming the electrically conductive contact structure comprises forming a contact trench of the transistor structure in the semiconductor substrate, the electrically conductive contact structure being in contact with the first doping region of the transistor structure and the body region of the transistor structure within the contact trench of the transistor structure.

15. The method of claim 9 , further comprising extending a compensation region of the plurality of compensation regions from a bottom of the gate trench structure into the semiconductor substrate.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Tegen Stefan
• Manger Dirk

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H01L21/823487

  Electricity · mapped topic

• H01L29/7811 Primary

  Electricity · mapped topic

• H01L21/823481

  Electricity · mapped topic