Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts

Patent metadata

Field	Value
Publication number	US-10608092-B2
Application number	US-201715844520-A
Country	US
Kind code	B2
Filing date	Dec 16, 2017
Priority date	Jun 1, 2010
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.

First claim

We claim:

1. A method of forming a shield gate trench (SGT) MOSFET with source body shorting silicide comprising:
forming trenches by applying a first photo mask with semiconductor protuberances in between;
forming a bottom dielectric layer in a bottom of the trench;
forming a shield electrode at the bottom of the trench on top of the bottom dielectric layer and forming a dielectric layer surrounding the shield electrode;
forming an inter-electrode-dielectric over the shield electrode;
forming an upper gate dielectric layer on an upper trench sidewalls;
forming a recessed gate electrode on top of the inter-electrode-dielectric layer surrounded by the upper gate dielectric layer;
forming source regions along the top surface of semiconductor protuberance sidewalls, using the recessed gate electrode as a mask;
forming a body region between and below source regions; and
forming a source/body silicide substantially across the entire top surface of the semiconductor protuberance;
forming contacts with a second photomask for contacting the source and body regions, and forming a source metal and a gate metal with a third photomask; and
wherein the steps of forming the source and body regions further comprising a step of applying an additional mask to protect a Schottky diode region.

2. The method of claim 1 further comprising a step of removing the top portion of the semiconductor protuberance to allow the source/body silicide to contact the body region between the source regions.

3. A method of forming a shield gate trench (SGT) MOSFET with source body shorting silicide comprising:
forming trenches by applying a first photo mask with semiconductor protuberances in between;
forming a bottom dielectric layer in a bottom of the trench;
forming a shield electrode at the bottom of the trench on top of the bottom dielectric layer and forming a dielectric layer surrounding the shield electrode;
forming an inter-electrode-dielectric over the shield electrode;
forming an upper gate dielectric layer on an upper trench sidewalls;
forming a recessed gate electrode on top of the inter-electrode-dielectric layer surrounded by the upper gate dielectric layer;
forming source regions along the top surface of semiconductor protuberance sidewalls, using the recessed gate electrode as a mask;
forming a body region between and below source regions;
forming a source/body silicide substantially across the entire top surface of the semiconductor protuberance;
forming contacts with a second photomask for contacting the source and body regions, and forming a source metal and a gate metal with a third photomask; and
using two additional masks for forming an ESD structure of back-to-back gate-source diodes.

4. The method of claim 3 further comprising a step of using an additional mask to protect a Schottky diode region while forming the source and body regions.

5. The method of claim 1 further comprising a step of applying two additional masks for forming an ESD structure of back-to-back gate-source diodes.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Yilmaz Hamza
• Chen John
• Ng Daniel
• Li Wenjun

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H01L29/66143

  Electricity · mapped topic

• H01L29/66674

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic